Jianfei Jiang

578 total citations
94 papers, 379 citations indexed

About

Jianfei Jiang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Jianfei Jiang has authored 94 papers receiving a total of 379 indexed citations (citations by other indexed papers that have themselves been cited), including 59 papers in Electrical and Electronic Engineering, 25 papers in Hardware and Architecture and 20 papers in Computer Networks and Communications. Recurrent topics in Jianfei Jiang's work include Quantum and electron transport phenomena (15 papers), Interconnection Networks and Systems (15 papers) and Parallel Computing and Optimization Techniques (14 papers). Jianfei Jiang is often cited by papers focused on Quantum and electron transport phenomena (15 papers), Interconnection Networks and Systems (15 papers) and Parallel Computing and Optimization Techniques (14 papers). Jianfei Jiang collaborates with scholars based in China, United States and Netherlands. Jianfei Jiang's co-authors include Zhigang Mao, Naifeng Jing, Weiguang Sheng, Guanghui He, Qin Wang, Qing Cai, Weifeng He, Chin‐Hwa Hu, Qin Wang and Sorin Cotöfană and has published in prestigious journals such as Journal of the American Chemical Society, Applied Physics Letters and Expert Systems with Applications.

In The Last Decade

Jianfei Jiang

76 papers receiving 365 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Jianfei Jiang China 11 228 93 65 60 57 94 379
Patrick Garda France 10 156 0.7× 75 0.8× 26 0.4× 19 0.3× 15 0.3× 82 329
Rajesh Garg United States 13 365 1.6× 100 1.1× 215 3.3× 34 0.6× 14 0.2× 46 547
Cyrus Bamji United States 10 256 1.1× 243 2.6× 106 1.6× 16 0.3× 28 0.5× 23 643
Zhaodong Chen China 12 142 0.6× 210 2.3× 55 0.8× 20 0.3× 17 0.3× 36 455
Dustin Richmond United States 9 101 0.4× 35 0.4× 115 1.8× 94 1.6× 14 0.2× 28 303
Daisuke Miyashita Japan 12 400 1.8× 112 1.2× 33 0.5× 46 0.8× 8 0.1× 35 501
Yue Jiang China 10 109 0.5× 113 1.2× 16 0.2× 28 0.5× 25 0.4× 48 312
Ramtin Zand United States 12 402 1.8× 23 0.2× 67 1.0× 26 0.4× 121 2.1× 54 487
K. Azadet United States 12 480 2.1× 29 0.3× 23 0.4× 70 1.2× 9 0.2× 44 546
Jose A. Belloch Spain 10 110 0.5× 60 0.6× 48 0.7× 33 0.6× 8 0.1× 53 300

Countries citing papers authored by Jianfei Jiang

Since Specialization
Citations

This map shows the geographic impact of Jianfei Jiang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jianfei Jiang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jianfei Jiang more than expected).

Fields of papers citing papers by Jianfei Jiang

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jianfei Jiang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jianfei Jiang. The network helps show where Jianfei Jiang may publish in the future.

Co-authorship network of co-authors of Jianfei Jiang

This figure shows the co-authorship network connecting the top 25 collaborators of Jianfei Jiang. A scholar is included among the top collaborators of Jianfei Jiang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jianfei Jiang. Jianfei Jiang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Jing, Naifeng, et al.. (2025). A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 33(6). 1502–1515.
2.
Li, Xiaoyan, et al.. (2025). Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 15(4). 599–608.
3.
Wang, Qin, et al.. (2024). A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. Expert Systems with Applications. 249. 123828–123828. 1 indexed citations
4.
5.
Liu, Siting, et al.. (2024). Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks. 1–6. 1 indexed citations
6.
Jiang, Jianfei, et al.. (2024). RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43(10). 2854–2867. 2 indexed citations
7.
8.
Zhang, Zihan, et al.. (2023). 3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43(1). 176–188. 3 indexed citations
9.
Chen, Zhuo, Zihan Zhang, Jianfei Jiang, et al.. (2023). ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. 28. 1–4. 1 indexed citations
10.
Wang, Qin, et al.. (2022). A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. IEEE Geoscience and Remote Sensing Letters. 19. 1–5. 10 indexed citations
11.
Jiang, Jianfei, et al.. (2022). An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30(11). 1587–1600. 16 indexed citations
12.
Jiang, Jianfei, et al.. (2022). A CPU-FPGA Heterogeneous Acceleration System for Scene Text Detection Network. IEEE Transactions on Circuits & Systems II Express Briefs. 69(6). 2947–2951. 9 indexed citations
13.
Zhang, Zihan, Jianfei Jiang, Yongxin Zhu, et al.. (2021). A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41(7). 2094–2106. 1 indexed citations
14.
Yin, Chen, Qin Wang, Jianfei Jiang, et al.. (2021). Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. 1394–1399. 4 indexed citations
15.
Wang, Qin, et al.. (2020). A Lightweight CNN for Low-Complexity HEVC Intra Encoder. 3 indexed citations
16.
He, Weifeng, Jianfei Jiang, Xuejun Zhao, et al.. (2017). A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. Integration. 58. 27–34. 3 indexed citations
17.
Jing, Naifeng, et al.. (2015). Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. International Conference on Computer Aided Design. 764–769.
18.
Cotöfană, Sorin, et al.. (2004). Analysis of analog to digital converter based on single-electron tunnelling transistors. III–693. 3 indexed citations
19.
20.
Yin, You, et al.. (2002). Scanning tunneling microscopy and in situ spectroscopy of ultra thin Ti films and nano sized TiOx dots induced by STM. Applied Surface Science. 199(1-4). 319–327. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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