J. Urresti

523 citations

34 papers · 420 indexed · h-index 12

Impact in

Electrical and Electronic Engineering top 10%
- Silicon Carbide Semiconductor Technologies
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Electrostatic Discharge in Electronics
- Electromagnetic Compatibility and Noise Suppression
- Multilevel Inverters and Converters
- Advanced DC-DC Converters
- Integrated Circuits and Semiconductor Failure Analysis
Electronic, Optical and Magnetic Materials

Papers in

Electrical and Electronic Engineering 34
- Silicon Carbide Semiconductor Technologies 31
- Semiconductor materials and devices 16
- Electrostatic Discharge in Electronics 13
- Advancements in Semiconductor Devices and Circuit Design 11
- Electromagnetic Compatibility and Noise Suppression 11
- Advanced DC-DC Converters 4
- Multilevel Inverters and Converters 4
- Thin-Film Transistor Technologies 3
Hardware and Architecture 1

Co-authors: J. Rebollo Nicolas G. Wright S. Hidalgo Alberto Castellazzi X. Perpiñà Michele Riccio Andrea Irace X. Jordà
Journals: Microelectronics Reliability (5 papers)Solid-State Electronics (3 papers)IEEE Electron Device Letters (2 papers)IEEE Transactions on Electron Devices (2 papers)Energies (1 paper)
Partner nations: Spain United Kingdom France

In The Last Decade

J. Urresti

33 papers receiving 400 citations

Peers

Countries citing papers authored by J. Urresti

Since Specialization

Citations

This map shows the geographic impact of J. Urresti's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Urresti with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Urresti more than expected).

Fields of papers citing papers by J. Urresti

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Urresti. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Urresti. The network helps show where J. Urresti may publish in the future.

Co-authors

The 25 scholars most cited alongside J. Urresti, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J. Urresti Line = papers co-authored together J. Urresti links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	High Mobility 4H-SiC MOSFET A.G. O’Neill, Faiz Arith, J. Urresti, Tae-Kyung Kim, Nicolas G. Wright, Sarah H. Olsen	2018	2
2	Increased Mobility in Enhancement Mode 4H-SiC MOSFET Using a Thin SiO₂/ Al₂O₃Gate Stack IEEE Electron Device Letters ·Faiz Arith, J. Urresti, Tae-Kyung Kim, Sarah H. Olsen, Nicolas G. Wright, A.G. O’Neill	2018	35
3	High-Mobility SiC MOSFETs Using a Thin-SiO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> Gate Stack Materials science forum ·J. Urresti, Faiz Arith, Konstantin Vassilevski, Amit Kumar Tiwari, Sarah H. Olsen, Nicolas G. Wright, A.G. O’Neill	2018	3
4	Characterisation of 4H-SiC MOS Capacitor with a Protective Coating for Harsh Environments Applications Materials science forum ·Sandip Kumar Roy, J. Urresti, A.G. O’Neill, Nicolas G. Wright, Alton B. Horsfall	2017	1
5	Transient out-of-SOA robustness of SiC power MOSFETs Alberto Castellazzi, Asad Fayyaz, G. Romano, Michele Riccio, Andrea Irace, J. Urresti, Nicolas G. Wright	2017	23
6	Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs Asad Fayyaz, Alberto Castellazzi, G. Romano, Michele Riccio, Andrea Irace, J. Urresti, Nicolas G. Wright	2017	14
7	3.3 kV PT‐IGBT with voltage‐sensor monolithically integrated IET Circuits Devices & Systems ·J. Urresti, S. Hidalgo, D. Flores, Daniel Fernández Hevia	2014	1
8	Layout Role in Failure Physics of IGBTs Under Overloading Clamped Inductive Turnoff IEEE Transactions on Electron Devices ·X. Perpiñà, Bandiyah Sri Aprilia, J. Urresti, X. Jordà, J. Rebollo	2012	23
9	Study of layout influence on ruggedness of NPT-IGBT devices by physical modelling Microelectronics Reliability ·(unknown), X. Perpiñà, J. Urresti, X. Jordà, J. Rebollo	2012	3
10	Edge termination impact on clamped inductive turn-off failure in high-voltage IGBTs under overcurrent conditions X. Perpiñà, (unknown), J. Urresti, X. Jordà, J. Rebollo, José del R. Millán	2011	7
11	Over-current turn-off failure in high voltage IGBT modules under clamped inductive load European Conference on Power Electronics and Applications ·X. Perpiñà, J Sentance, X. Jordà, S. Hidalgo, J. Urresti, J. Rebollo, Michel Mermet-Guyennet	2009	5
12	Lateral Punch-Through TVS Devices: Design and Fabrication J. Urresti, S. Hidalgo, D. Flores, J. Rebollo	2009	2
13	Non-uniform temperature and heat generation in thin-film SOI LDMOS with uniform drift doping IEE Proceedings - Circuits Devices and Systems ·J. Roig, D. Flores, (unknown), J. Urresti, S. Hidalgo, J. Rebollo, Eline Zweers	2006	1
14	A quasi-analytical breakdown voltage model in four-layer punch-through TVS devices Solid-State Electronics ·J. Urresti, S. Hidalgo, D. Flores, J. Roig, J. Rebollo, L Vera	2005	1
15	Degradation analysis in SOI LDMOS transistors with steep retrograde doping profile and source field plate (unknown), J. Roig, D. Flores, J. Urresti, S. Hidalgo, José del R. Millán	2005	3
16	A numerical study of field plate configurations in RF SOI LDMOS transistors Solid-State Electronics ·(unknown), J. Roig, D. Flores, J. Urresti, S. Hidalgo, J. Rebollo	2005	19
17	Efficiency of SOI-Like Structures for Reducing the Thermal Resistance in Thin-Film SOI Power LDMOSFETs IEEE Electron Device Letters ·J. Roig, J. Urresti, (unknown), D. Flores, S. Hidalgo, José del R. Millán	2004	4
18	Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile Microelectronics Reliability ·(unknown), J. Roig, D. Flores, J. Urresti, S. Hidalgo, J. Rebollo	2004	30
19	Modeling of non-uniform heat generation in LDMOS transistors Solid-State Electronics ·J. Roig, D. Flores, J. Urresti, S. Hidalgo, J. Rebollo	2004	9
20	Lateral punch-through TVS devices for on-chip protection in low-voltage applications Microelectronics Reliability ·J. Urresti, S. Hidalgo, D. Flores, J. Roig, (unknown), J. Rebollo	2004	6

About J. Urresti

J. Urresti is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Electronic, Optical and Magnetic Materials, Control and Systems Engineering and Mechanical Engineering, having authored 34 papers that have together received 420 indexed citations. Recurring topics across this work include Silicon Carbide Semiconductor Technologies (31 papers), Semiconductor materials and devices (16 papers), Electrostatic Discharge in Electronics (13 papers), Advancements in Semiconductor Devices and Circuit Design (11 papers), Electromagnetic Compatibility and Noise Suppression (11 papers), Advanced DC-DC Converters (4 papers), Multilevel Inverters and Converters (4 papers) and Thin-Film Transistor Technologies (3 papers). The work is most often cited by research in Electrical and Electronic Engineering (411 citations), Electronic, Optical and Magnetic Materials (17 citations), Control and Systems Engineering (21 citations), Condensed Matter Physics (10 citations) and Mechanical Engineering (26 citations). J. Urresti has collaborated with scholars based in Spain, United Kingdom and France. Frequent co-authors include J. Rebollo, Nicolas G. Wright, S. Hidalgo, Alberto Castellazzi, X. Perpiñà, Michele Riccio, Andrea Irace, X. Jordà, G. Romano and Asad Fayyaz. Their work appears in journals such as Microelectronics Reliability, Solid-State Electronics, IEEE Electron Device Letters, IEEE Transactions on Electron Devices and Energies.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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