J. Grodstein

421 total citations
22 papers, 209 citations indexed

About

J. Grodstein is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, J. Grodstein has authored 22 papers receiving a total of 209 indexed citations (citations by other indexed papers that have themselves been cited), including 20 papers in Hardware and Architecture, 20 papers in Electrical and Electronic Engineering and 2 papers in Computer Networks and Communications. Recurrent topics in J. Grodstein's work include Low-power high-performance VLSI design (18 papers), VLSI and Analog Circuit Testing (17 papers) and VLSI and FPGA Design Techniques (9 papers). J. Grodstein is often cited by papers focused on Low-power high-performance VLSI design (18 papers), VLSI and Analog Circuit Testing (17 papers) and VLSI and FPGA Design Techniques (9 papers). J. Grodstein collaborates with scholars based in United States and Germany. J. Grodstein's co-authors include Eric Lehman, Y. Watanabe, R. Iris Bahar, Bill Grundmann, H.J. Touati, Kundan Nepal, Richard Davies, D.K. Bhavsar, Larry Biro and Rahul Razdan and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Journal of Electronic Testing and International Conference on Computer Aided Design.

In The Last Decade

J. Grodstein

21 papers receiving 195 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
J. Grodstein United States	8	178	152	31	25	10	22	209
Andrew Sullivan United States	7	187 1.1×	158 1.0×	17 0.5×	25 1.0×	11 1.1×	15	211
K.D. Wagner United States	8	220 1.2×	233 1.5×	15 0.5×	20 0.8×	13 1.3×	12	260
Yuji Kukimoto United States	9	151 0.8×	143 0.9×	57 1.8×	8 0.3×	12 1.2×	15	190
Ku He United States	9	323 1.8×	82 0.5×	21 0.7×	15 0.6×	6 0.6×	14	335
Sobeeh Almukhaizim United States	12	319 1.8×	280 1.8×	13 0.4×	34 1.4×	11 1.1×	37	336
D. Plass United States	10	276 1.6×	151 1.0×	12 0.4×	61 2.4×	6 0.6×	16	319
A. Agarwal United States	8	508 2.9×	382 2.5×	14 0.5×	34 1.4×	4 0.4×	9	539
Masaki Hashizume Japan	8	215 1.2×	158 1.0×	8 0.3×	12 0.5×	7 0.7×	100	236
S. Rotem United States	8	192 1.1×	202 1.3×	74 2.4×	73 2.9×	18 1.8×	11	266
Ashish Srivastava United States	5	339 1.9×	185 1.2×	7 0.2×	27 1.1×	16 1.6×	12	381

Countries citing papers authored by J. Grodstein

Since Specialization

Citations

This map shows the geographic impact of J. Grodstein's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Grodstein with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Grodstein more than expected).

Fields of papers citing papers by J. Grodstein

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Grodstein. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Grodstein. The network helps show where J. Grodstein may publish in the future.

Co-authorship network of co-authors of J. Grodstein

This figure shows the co-authorship network connecting the top 25 collaborators of J. Grodstein. A scholar is included among the top collaborators of J. Grodstein based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with J. Grodstein. J. Grodstein is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

1.

Bahar, R. Iris, et al.. (2011). Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. Journal of Electronic Testing. 27(2). 123–136. 5 indexed citations

2.

Grodstein, J., et al.. (2009). AutoRex: An automated post-silicon clock tuning tool. 1. 1–10. 15 indexed citations

3.

Bahar, R. Iris, et al.. (2007). Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models. 1–6. 4 indexed citations

4.

Nepal, Kundan, et al.. (2006). Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25(9). 1815–1830. 5 indexed citations

5.

Bahar, R. Iris, et al.. (2005). Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24(4). 502–515. 5 indexed citations

6.

Bahar, R. Iris, et al.. (2004). Symbolic failure analysis of custom circuits due to excessive leakage current. 70–75. 1 indexed citations

7.

Grodstein, J., et al.. (2004). Automatic generation of critical-path tests for a partial-scan microprocessor. 180–186. 8 indexed citations

8.

Nepal, Kundan, et al.. (2004). RESTA. 407–412. 5 indexed citations

9.

Grodstein, J., et al.. (2002). A delay model for logic synthesis of continuously-sized networks. 458–462. 13 indexed citations

10.

Grodstein, J., et al.. (2002). Constraint identification for timing verification. 16–19. 4 indexed citations

11.

Bahar, R. Iris, et al.. (2002). Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations.. 203–208. 1 indexed citations

12.

Grodstein, J., et al.. (2002). Static race verification for networks with reconvergent clocks. 524–529. 1 indexed citations

13.

Grodstein, J., et al.. (2002). Automatic detection of MOS synchronizers for timing verification. 304–307. 2 indexed citations

14.

Lehman, Eric, et al.. (1997). Logic decomposition during technology mapping. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 16(8). 813–834. 58 indexed citations

15.

Grodstein, J., et al.. (1995). A delay model for logic synthesis of continuously-sized networks. International Conference on Computer Aided Design. 458–462. 28 indexed citations

16.

Grodstein, J., et al.. (1994). Optimal latch mapping and retiming within a tree. International Conference on Computer Aided Design. 242–245. 5 indexed citations

17.

Grodstein, J., et al.. (1993). A simple algorithm for fanout optimization using high-performance buffer libraries. International Conference on Computer Aided Design. 466–471. 12 indexed citations

18.

Biro, Larry, et al.. (1991). Timing verification on a 1.2M-device full-custom CMOS design. 551–554. 5 indexed citations

19.

Allmon, R., B.J. Benschneider, Ling Chao, et al.. (1990). System, process, and design implications of a reduced supply voltage microprocessor. 48–49. 9 indexed citations

20.

Grodstein, J., et al.. (1990). Race detection for two-phase systems. 20–23. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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