D. Plass

779 total citations
16 papers, 319 citations indexed

About

D. Plass is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, D. Plass has authored 16 papers receiving a total of 319 indexed citations (citations by other indexed papers that have themselves been cited), including 16 papers in Electrical and Electronic Engineering, 6 papers in Hardware and Architecture and 1 paper in Computer Networks and Communications. Recurrent topics in D. Plass's work include Low-power high-performance VLSI design (13 papers), Semiconductor materials and devices (12 papers) and Advancements in Semiconductor Devices and Circuit Design (7 papers). D. Plass is often cited by papers focused on Low-power high-performance VLSI design (13 papers), Semiconductor materials and devices (12 papers) and Advancements in Semiconductor Devices and Circuit Design (7 papers). D. Plass collaborates with scholars based in United States, Germany and Taiwan. D. Plass's co-authors include Y.H. Chan, Ching-Te Chuang, Eric Fluhr, Joshua Friedrich, A. Devgan, W. Huott, J. DiLullo, Pramod Kumar Patel, Subhas Chandra Mukhopadhyay and Rajiv Joshi and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and IBM Journal of Research and Development.

In The Last Decade

D. Plass

16 papers receiving 309 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
D. Plass United States	10	276	151	61	12	10	16	319
Eric Fluhr United States	9	213 0.8×	160 1.1×	65 1.1×	13 1.1×	20 2.0×	17	273
Daniel B. Jackson United States	6	238 0.9×	183 1.2×	94 1.5×	6 0.5×	9 0.9×	15	326
Ana Sonia Leon United States	8	197 0.7×	200 1.3×	156 2.6×	6 0.5×	13 1.3×	12	298
Leomar S. da Rosa Brazil	9	243 0.9×	115 0.8×	40 0.7×	11 0.9×	15 1.5×	56	273
D. Ayers United States	8	314 1.1×	267 1.8×	147 2.4×	5 0.4×	14 1.4×	13	408
Robert Giterman Israel	11	367 1.3×	103 0.7×	56 0.9×	7 0.6×	11 1.1×	36	390
Gyoyoung Jin South Korea	7	193 0.7×	42 0.3×	61 1.0×	9 0.8×	13 1.3×	25	221
Philippe Magarshack France	6	159 0.6×	123 0.8×	108 1.8×	3 0.3×	13 1.3×	14	225
D.H. Allen United States	6	335 1.2×	176 1.2×	89 1.5×	5 0.4×	30 3.0×	9	368
W.K. Luk United States	9	293 1.1×	155 1.0×	81 1.3×	17 1.4×	11 1.1×	22	327

Countries citing papers authored by D. Plass

Since Specialization

Citations

This map shows the geographic impact of D. Plass's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Plass with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Plass more than expected).

Fields of papers citing papers by D. Plass

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Plass. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Plass. The network helps show where D. Plass may publish in the future.

Co-authorship network of co-authors of D. Plass

This figure shows the co-authorship network connecting the top 25 collaborators of D. Plass. A scholar is included among the top collaborators of D. Plass based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with D. Plass. D. Plass is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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16 of 16 papers shown

1.

Fluhr, Eric, Daniel Dreps, Rahul Rao, et al.. (2017). 3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. 50–51. 13 indexed citations

2.

Plass, D., et al.. (2015). 17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. 6 indexed citations

3.

Fluhr, Eric, Joshua Friedrich, Daniel Dreps, et al.. (2014). 5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. 96–97. 33 indexed citations

4.

Joshi, Rajiv, Saibal Mukhopadhyay, D. Plass, et al.. (2009). Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. IEEE Journal of Solid-State Circuits. 44(3). 965–976. 22 indexed citations

5.

Barth, J., Fadi H. Gebara, J.D. Schaub, et al.. (2008). An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. 66–69. 3 indexed citations

6.

Joshi, Rahul, R. Houle, Pramod Kumar Patel, et al.. (2008). A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities. 208–209. 5 indexed citations

7.

Houle, R., Pramod Kumar Patel, W. Huott, et al.. (2007). 6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM. 250–251. 43 indexed citations

8.

Plass, D. & Y.H. Chan. (2007). IBM POWER6 SRAM arrays. IBM Journal of Research and Development. 51(6). 747–756. 18 indexed citations

9.

Friedrich, Joshua, B.D. McCredie, N. James, et al.. (2007). Design of the Power6 Microprocessor. 96–97. 86 indexed citations

10.

Joshi, Rajiv, Rouwaida Kanj, Sani Nassif, et al.. (2006). Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell. 315–318. 15 indexed citations

11.

Davis, John D., D. Plass, Rahul Joshi, et al.. (2006). A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. 2564–2571. 16 indexed citations

12.

Chan, Y.H., et al.. (2006). A Low Power and High Performance SOI SRAM Circuit Design with Improved Cell Stability. 38. 4–7. 9 indexed citations

13.

Mukhopadhyay, Subhas Chandra, et al.. (2004). Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. 211–214. 38 indexed citations

14.

Clabes, J., Joshua Friedrich, M. Sweet, et al.. (2004). Design and Implementation of the POWER5 TM Microprocessor. 9 indexed citations

15.

Reohr, W., et al.. (2002). Design SRAMs for burn-in. 164–170. 2 indexed citations

16.

Davis, John D., et al.. (2002). Design validation of .18 μm 1 GHz cache and register arrays. 295–298. 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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