H.T. Vergos

1.2k total citations
63 papers, 862 citations indexed

About

H.T. Vergos is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Information Systems. According to data from OpenAlex, H.T. Vergos has authored 63 papers receiving a total of 862 indexed citations (citations by other indexed papers that have themselves been cited), including 54 papers in Electrical and Electronic Engineering, 30 papers in Hardware and Architecture and 23 papers in Information Systems. Recurrent topics in H.T. Vergos's work include Low-power high-performance VLSI design (42 papers), VLSI and Analog Circuit Testing (25 papers) and Cryptography and Residue Arithmetic (23 papers). H.T. Vergos is often cited by papers focused on Low-power high-performance VLSI design (42 papers), VLSI and Analog Circuit Testing (25 papers) and Cryptography and Residue Arithmetic (23 papers). H.T. Vergos collaborates with scholars based in Greece and United States. H.T. Vergos's co-authors include C. Efstathiou, D. Nikolos, Giorgos Dimitrakopoulos, John Kalamatianos, L. Kalampoukas, Dimitris Nikolos, George Alexiou, Xrysovalantis Kavousianos, Emmanouil Kalligeros and Yiorgos Tsiatouhas and has published in prestigious journals such as IEEE Transactions on Computers, IEEE Transactions on Circuits & Systems II Express Briefs and Journal of Systems Architecture.

In The Last Decade

H.T. Vergos

60 papers receiving 820 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
H.T. Vergos Greece 14 551 542 486 257 210 63 862
S.J. Piestrak Poland 13 416 0.8× 271 0.5× 396 0.8× 131 0.5× 149 0.7× 40 633
Ahmad Hiasat Jordan 14 467 0.8× 223 0.4× 439 0.9× 149 0.6× 52 0.2× 42 601
D. Nikolos Greece 17 411 0.7× 905 1.7× 413 0.8× 229 0.9× 622 3.0× 92 1.2k
Richard I. Tanaka 2 479 0.9× 232 0.4× 394 0.8× 233 0.9× 108 0.5× 3 674
Laurent Imbert France 12 324 0.6× 113 0.2× 348 0.7× 138 0.5× 50 0.2× 46 524
A.F. Tenca United States 12 341 0.6× 116 0.2× 343 0.7× 107 0.4× 46 0.2× 37 517
M.O. Ahmad Canada 10 239 0.4× 121 0.2× 219 0.5× 88 0.3× 37 0.2× 34 376
Nagisa Ishiura Japan 14 95 0.2× 268 0.5× 143 0.3× 422 1.6× 403 1.9× 53 767
Stelios Sidiroglou-Douskos United States 12 229 0.4× 270 0.5× 355 0.7× 42 0.2× 306 1.5× 20 865
Shobha Vasudevan United States 14 108 0.2× 292 0.5× 113 0.2× 267 1.0× 382 1.8× 58 652

Countries citing papers authored by H.T. Vergos

Since Specialization
Citations

This map shows the geographic impact of H.T. Vergos's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by H.T. Vergos with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites H.T. Vergos more than expected).

Fields of papers citing papers by H.T. Vergos

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by H.T. Vergos. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by H.T. Vergos. The network helps show where H.T. Vergos may publish in the future.

Co-authorship network of co-authors of H.T. Vergos

This figure shows the co-authorship network connecting the top 25 collaborators of H.T. Vergos. A scholar is included among the top collaborators of H.T. Vergos based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with H.T. Vergos. H.T. Vergos is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Vergos, H.T., et al.. (2016). Extending the viability of power signature — Based IP watermarking in the SoC era. 281–284. 2 indexed citations
2.
Vergos, H.T., et al.. (2014). Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. Circuits Systems and Signal Processing. 34(4). 1041–1056. 1 indexed citations
3.
Vergos, H.T., et al.. (2013). Fast parallel-prefix Ling-carry adders in QCA nanotechnology. 565–568. 1 indexed citations
4.
Vergos, H.T., et al.. (2011). On the use of double-LSB and signed-LSB encodings for RNS. 1–6. 1 indexed citations
5.
Vergos, H.T., et al.. (2010). SUT-RNS Forward and Reverse Converters. 2823. 11–16.
6.
Vergos, H.T., et al.. (2009). Novel modulo 2n+1 subtractors.. DPS. 1–5. 2 indexed citations
7.
Vergos, H.T., et al.. (2009). Novel modulo 2<sup>n</sup>+1 subtractors. 33. 1–5. 1 indexed citations
8.
Vergos, H.T., et al.. (2008). Efficient modulo 2<sup>n</sup> + 1 multi-operand adders. 694–697. 3 indexed citations
9.
Vergos, H.T. & C. Efstathiou. (2008). A Unifying Approach for Weighted and Diminished-1 Modulo $2^n+1$ Addition. IEEE Transactions on Circuits & Systems II Express Briefs. 55(10). 1041–1045. 32 indexed citations
10.
Vergos, H.T.. (2007). An Efficient BIST Scheme for Non-Restoring Array Dividers. 664–667. 2 indexed citations
11.
Vergos, H.T. & C. Efstathiou. (2007). Design of efficient modulo 2 n +1 multipliers. IET Computers & Digital Techniques. 1(1). 49–57. 49 indexed citations
12.
Vergos, H.T., et al.. (2006). KoVer: A Sophisticated Residue Arithmetic Core Generator. 261–263. 1 indexed citations
13.
Dimitrakopoulos, Giorgos, D. Nikolos, H.T. Vergos, & C. Efstathiou. (2005). New architectures for modulo 2N - 1 adders. 1–4. 25 indexed citations
14.
Efstathiou, C., et al.. (2004). Efficient modulo 2/sup n/+1 tree multipliers for diminished-1 operands. 47. 200–203. 2 indexed citations
15.
Vergos, H.T., et al.. (2003). Path delay fault testing of Benes multistage interconnection networks. 2. 1097–1100.
16.
Kalligeros, Emmanouil, et al.. (2002). On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. Journal of Systems Architecture. 48(4-5). 125–135. 6 indexed citations
17.
Efstathiou, C. & H.T. Vergos. (2002). Modified Booth 1's complement and modulo 2/sup n/-1 multipliers. 2. 637–640. 6 indexed citations
18.
Haniotakis, Themistoklis, et al.. (2002). A class of easily path delay fault testable circuits. 165–170. 1 indexed citations
19.
Kavousianos, Xrysovalantis, et al.. (2001). Low Power Built‐In Self‐Test Schemes for Array and Booth Multipliers. VLSI design. 12(3). 431–448. 1 indexed citations
20.
Nikolos, D. & H.T. Vergos. (1999). On the yield of VLSI processors with on-chip CPU cache. IEEE Transactions on Computers. 48(10). 1138–1144. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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