Ashis Kumar Mal

466 total citations
73 papers, 286 citations indexed

About

Ashis Kumar Mal is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Ashis Kumar Mal has authored 73 papers receiving a total of 286 indexed citations (citations by other indexed papers that have themselves been cited), including 69 papers in Electrical and Electronic Engineering, 34 papers in Biomedical Engineering and 10 papers in Hardware and Architecture. Recurrent topics in Ashis Kumar Mal's work include Analog and Mixed-Signal Circuit Design (31 papers), Low-power high-performance VLSI design (29 papers) and VLSI and FPGA Design Techniques (21 papers). Ashis Kumar Mal is often cited by papers focused on Analog and Mixed-Signal Circuit Design (31 papers), Low-power high-performance VLSI design (29 papers) and VLSI and FPGA Design Techniques (21 papers). Ashis Kumar Mal collaborates with scholars based in India, Nepal and Czechia. Ashis Kumar Mal's co-authors include Rajib Kar, Anindya Sundar Dhar, Rajat Mahapatra, Arindam Basu, A. K. Bhattacharjee, Durbadal Mandal, Sujit Mandal, Shankar Prakriya, Anirban Karmakar and Narendra Nath Ghosh and has published in prestigious journals such as IEEE Transactions on Wireless Communications, Computers & Electrical Engineering and Wireless Personal Communications.

In The Last Decade

Ashis Kumar Mal

66 papers receiving 271 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Ashis Kumar Mal India 9 249 128 38 32 26 73 286
Min-Sun Keel United States 10 407 1.6× 122 1.0× 33 0.9× 4 0.1× 61 2.3× 18 464
Kimmo Koli Finland 11 357 1.4× 245 1.9× 8 0.2× 9 0.3× 12 0.5× 48 391
M. Shams Canada 8 265 1.1× 86 0.7× 26 0.7× 12 0.4× 80 3.1× 23 304
Abu Khari A’ain Malaysia 10 285 1.1× 147 1.1× 15 0.4× 4 0.1× 28 1.1× 53 318
Youngjoon Kim South Korea 9 331 1.3× 117 0.9× 31 0.8× 31 1.0× 45 1.7× 28 382
Guangsheng Liang United States 6 272 1.1× 249 1.9× 25 0.7× 5 0.2× 9 0.3× 12 330
A. Eshraghi United States 9 292 1.2× 227 1.8× 7 0.2× 47 1.5× 12 0.5× 16 328
Jeffrey Gealow United States 9 324 1.3× 268 2.1× 13 0.3× 18 0.6× 16 0.6× 12 358
Wilfred Gomes United States 8 194 0.8× 31 0.2× 19 0.5× 8 0.3× 76 2.9× 13 273
Martin Andraud Belgium 8 191 0.8× 114 0.9× 18 0.5× 4 0.1× 41 1.6× 27 218

Countries citing papers authored by Ashis Kumar Mal

Since Specialization
Citations

This map shows the geographic impact of Ashis Kumar Mal's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ashis Kumar Mal with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ashis Kumar Mal more than expected).

Fields of papers citing papers by Ashis Kumar Mal

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ashis Kumar Mal. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ashis Kumar Mal. The network helps show where Ashis Kumar Mal may publish in the future.

Co-authorship network of co-authors of Ashis Kumar Mal

This figure shows the co-authorship network connecting the top 25 collaborators of Ashis Kumar Mal. A scholar is included among the top collaborators of Ashis Kumar Mal based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ashis Kumar Mal. Ashis Kumar Mal is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Mal, Ashis Kumar, et al.. (2024). A Survey on Hardware Accelerator Design of Deep Learning for Edge Devices. Wireless Personal Communications. 137(3). 1715–1760. 4 indexed citations
2.
Prakriya, Shankar, et al.. (2022). Cooperative Mode Switching-Based Cognitive NOMA With Transmit Antenna and User Selection. IEEE Transactions on Signal and Information Processing over Networks. 8. 932–945. 4 indexed citations
3.
Prakriya, Shankar, et al.. (2022). Performance of Novel Adaptive Schemes for Cognitive Full-Duplex Relaying-Based Downlink Cooperative NOMA. IEEE Transactions on Wireless Communications. 22(5). 3161–3179. 11 indexed citations
4.
Mal, Ashis Kumar, et al.. (2021). A cost-effective alertness-rating tool to enable situational awareness among on-duty static security guards in Covid-19 pandemic. Journal of Reliable Intelligent Environments. 7(4). 341–353. 1 indexed citations
5.
Mal, Ashis Kumar, et al.. (2020). An efficient method to compute simplified noise parameters of analog amplifiers using symbolic and evolutionary approach. International Journal of Numerical Modelling Electronic Networks Devices and Fields. 34(1). 2 indexed citations
6.
Mal, Ashis Kumar, et al.. (2019). A cost-effective system for triggering alarm to distracted drivers/ nurses. Computers & Electrical Engineering. 76. 24–39. 2 indexed citations
7.
Kar, Rajib, et al.. (2019). Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach. Computers & Electrical Engineering. 80. 106485–106485. 10 indexed citations
8.
Mal, Ashis Kumar, et al.. (2018). All MOS noise-shaped time-mode temperature sensor. Integration. 65. 74–80. 5 indexed citations
9.
10.
Basu, Saikat, et al.. (2011). Uncoercibility In E-Voting And E-Auctioning Mechanisms Using Deniable Encryption. International Journal of Network Security & Its Applications. 3(2). 97–109. 4 indexed citations
11.
Mal, Ashis Kumar, et al.. (2011). A low voltage high output impedance bulk driven regulated cascode current mirror. 3. 79–83. 6 indexed citations
12.
13.
Kar, Rajib, et al.. (2010). Closed Form Bandwidth Expression for Distributed On-chip RLCG Interconnects. 13. 144–147. 1 indexed citations
14.
15.
Kar, Rajib, et al.. (2010). A Novel and Efficient Approach for RC Delay Evaluation of On-chip VLSI Interconnect under Current Mode Signaling Technique. International Journal of Computer Applications. 1(10). 84–87. 4 indexed citations
16.
17.
Kar, Rajib, et al.. (2008). Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function. 1–3. 2 indexed citations
18.
Mal, Ashis Kumar & Anindya Sundar Dhar. (2004). Analog VLSI architecture for discrete cosine transform using dynamic switched capacitors. 666–669. 2 indexed citations
19.
Mal, Ashis Kumar & Anindya Sundar Dhar. (2004). Switched capacitor architecture for prime length discrete Hartley transform. e82 a. 505–508. 2 indexed citations
20.
Mal, Ashis Kumar & Anindya Sundar Dhar. (2003). Analog sampled data architecture for discrete Hartley transform. e82 a. 1035–1039 Vol.3. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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