Anees Ullah

623 citations

43 papers · 357 indexed · h-index 13

Impact in

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing
- Network Packet Processing and Optimization
- Embedded Systems Design Techniques
- Physical Unclonable Functions (PUFs) and Hardware Security
Computer Networks and Communications top 10%
- Interconnection Networks and Systems
- Software-Defined Networks and 5G

Papers in ⓘ

Electrical and Electronic Engineering 30
- Radiation Effects in Electronics 25
- Low-power high-performance VLSI design 10
Hardware and Architecture 25
- VLSI and Analog Circuit Testing 16
- Physical Unclonable Functions (PUFs) and Hardware Security 8
- Network Packet Processing and Optimization 7

Co-authors: Pedro Reviriego (28 shared papers)Luca Sterpone (8 shared papers)Salvatore Pontarelli (4 shared papers)Juan Antonio Maestro (4 shared papers)M. Sonza Reorda (2 shared papers)Alexis Ramos (2 shared papers)Zhen Gao (3 shared papers)Ernesto Sánchez (2 shared papers)
Journals: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (6 papers)IEEE Transactions on Circuits and Systems I Regular Papers (4 papers)Microelectronics Reliability (4 papers)Electronics (3 papers)IEEE Transactions on Device and Materials Reliability (3 papers)
Partner nations: Pakistan Spain Italy

In The Last Decade

Anees Ullah

39 papers receiving 341 citations

Peers

Countries citing papers authored by Anees Ullah

Since Specialization

Citations

This map shows the geographic impact of Anees Ullah's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Anees Ullah with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Anees Ullah more than expected).

Fields of papers citing papers by Anees Ullah

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Anees Ullah. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Anees Ullah. The network helps show where Anees Ullah may publish in the future.

Co-authors

The 25 scholars most cited alongside Anees Ullah, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Anees Ullah Line = papers co-authored together Anees Ullah links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 43 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation IEEE Transactions on Circuits and Systems I Regular Papers ·Uzma M. Butt, Shoab A. Khan, Anees Ullah, Abdul Khaliq, Pedro Reviriego, Ali Zahir	2021	25
2	PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Pedro Reviriego, Anees Ullah, Salvatore Pontarelli	2019	22
3	Majority Voting-Based Reduced Precision Redundancy Adders IEEE Transactions on Device and Materials Reliability ·Anees Ullah, Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro	2017	22
4	On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs Luca Sterpone, Anees Ullah	2013	21
5	An error-detection and self-repairing method for dynamically and partially reconfigurable systems PORTO Publications Open Repository TOrino (Politecnico di Torino) ·M. Sonza Reorda, Luca Sterpone, Anees Ullah	2013	20
6	Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Zhen Gao, Han Zhang, Yi Yao, Jiajun Xiao, Shulin Zeng, Guangjun Ge, Yu Wang, Anees Ullah, Pedro Reviriego	2022	19
7	An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems IEEE Transactions on Computers ·M. Sonza Reorda, Luca Sterpone, Anees Ullah	2016	18
8	An Efficient Methodology for On-Chip SEU Injection in Flip-Flops for Xilinx FPGAs IEEE Transactions on Nuclear Science ·Anees Ullah, Pedro Reviriego, Juan Antonio Maestro	2018	18
9	Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs IEEE Transactions on Computers ·Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro	2017	17
10	Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs IEEE Transactions on Nanotechnology ·Zhen Gao, Jinhua Zhu, Ruishi Han, Zhan Xu, Anees Ullah, Pedro Reviriego	2019	15
11	Improving the Hardware Complexity by Exploiting the Reduced Dynamics-Based Fractional Order Systems IEEE Access ·Nasim Ullah, Anees Ullah, Asier Ibeas, Jorge Herrera	2017	14
12	Intelligent Energy-Based Modified Super Twisting Algorithm and Factional Order PID Control for Performance Improvement of PMSG Dedicated to Tidal Power System IEEE Access ·Youcef Belkhier, Abdelyazid Achour, Nasim Ullah, Rabindra Nath Shaw, Zaheer Farooq, Anees Ullah, Ali Alzaed	2021	14
13	An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs Microelectronics Reliability ·Anees Ullah, Ernesto Sánchez, Luca Sterpone, L.A. Cardona, Carles Ferrer	2017	12
14	Error Detection and Correction in SRAM Emulated TCAMs IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Pedro Reviriego, Salvatore Pontarelli, Anees Ullah	2018	12
15	Low delay Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes Microelectronics Reliability ·Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Zhaochi Liu, Linzhe Li, Anees Ullah	2019	11
16	Reliability evaluation of FPGA based pruned neural networks Microelectronics Reliability ·Zhen Gao, Yi Yao, Xiaohui Wei, Yan Tong, Shulin Zeng, Guangjun Ge, Yu Wang, Anees Ullah, Pedro Reviriego	2022	10
17	Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Zhen Gao, Lingling Zhang, Yinghao Cheng, Kangkang Guo, Anees Ullah, Pedro Reviriego	2021	9
18	Systematic Reliability Evaluation of FPGA Implemented CNN Accelerators IEEE Transactions on Device and Materials Reliability ·Zhen Gao, Shihui Gao, Yi Yao, Qiang Liu, Shulin Zeng, Guangjun Ge, Yu Wang, Anees Ullah, Pedro Reviriego	2023	8
19	FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Ali Zahir, Shadan Khattak, Anees Ullah, Pedro Reviriego, Fahad Bin Muslim, Waleed Ahmad	2020	7
20	Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs Ernesto Sánchez, Luca Sterpone, Anees Ullah	2014	7

About Anees Ullah

Anees Ullah is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Computer Networks and Communications, Artificial Intelligence and Signal Processing, having authored 43 papers that have together received 357 indexed citations. Recurring topics across this work include Radiation Effects in Electronics (25 papers), VLSI and Analog Circuit Testing (16 papers), Low-power high-performance VLSI design (10 papers), Physical Unclonable Functions (PUFs) and Hardware Security (8 papers), Network Packet Processing and Optimization (7 papers), Network Security and Intrusion Detection (5 papers), Interconnection Networks and Systems (4 papers) and Cryptographic Implementations and Security (3 papers). The work is most often cited by research in Hardware and Architecture (175 citations), Computer Networks and Communications (99 citations), Electrical and Electronic Engineering (239 citations), Signal Processing (27 citations) and Software (9 citations). Anees Ullah has collaborated with scholars based in Pakistan, Spain and Italy. Frequent co-authors include Pedro Reviriego, Luca Sterpone, Salvatore Pontarelli, Juan Antonio Maestro, M. Sonza Reorda, Alexis Ramos, Zhen Gao, Ernesto Sánchez, Zhen Gao and Jorge Herrera. Their work appears in journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Circuits and Systems I Regular Papers, Microelectronics Reliability, Electronics and IEEE Transactions on Device and Materials Reliability.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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