Ameya D. Patil
- Hardware and Architecture top 10%
- Embedded Systems Design Techniques 1
-
- Advanced Memory and Neural Computing 8
- Ferroelectric and Negative Capacitance Devices 6
- Low-power high-performance VLSI design 3
- Advancements in Semiconductor Devices and Circuit Design 2
- Semiconductor materials and devices 2
-
- Stochastic Gradient Optimization Techniques 1
- Neural Networks and Applications 1
- Co-authors
- Naresh R. ShanbhagMingu KangSujan K. GonugondlaYongjune KimHaocheng HuaNaveen VermaLav R. VarshneyCharbel Sakr
- Journals
- Proceedings of the IEEE (1 paper)IEEE Journal of Solid-State Circuits (1 paper)IEEE Transactions on Circuits and Systems I Regular Papers (1 paper)
- Partner nations
- United StatesPortugalGermany
In The Last Decade
Ameya D. Patil
9 papers receiving 259 citations
Peers
Comparison fields: 5 of 32
- Hardware and Architecture 40
- Electrical and Electronic Engineering 233
- Artificial Intelligence 69
- Computer Vision and Pattern Recognition 35
- Computer Networks and Communications 28
Countries citing papers authored by Ameya D. Patil
This map shows the geographic impact of Ameya D. Patil's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ameya D. Patil with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ameya D. Patil more than expected).
Fields of papers citing papers by Ameya D. Patil
This network shows the impact of papers produced by Ameya D. Patil. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ameya D. Patil. The network helps show where Ameya D. Patil may publish in the future.
Co-authorship network
The 18 scholars most cited alongside Ameya D. Patil, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2025 | 0 | |
| 2 | 2022 | 6 | |
| 3 | 2020 | 5 | |
| 4 | 2020 | 13 | |
| 5 | 2019 | 2 | |
| 6 | 2019 | 0 | |
| 7 | Prognostication of breast cancer using data mining and machine learning | 2019 | 2 |
| 8 | 2019 | 39 | |
| 9 | 2018 | 26 | |
| 10 | 2018 | 160 | |
| 11 | 2017 | 12 | |
| 12 | 2017 | 0 |
About Ameya D. Patil
Ameya D. Patil is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Vision and Pattern Recognition, having authored 12 papers that have together received 265 indexed citations. Recurring topics across this work include Advanced Memory and Neural Computing (8 papers), Ferroelectric and Negative Capacitance Devices (6 papers), Low-power high-performance VLSI design (3 papers), Advancements in Semiconductor Devices and Circuit Design (2 papers), Semiconductor materials and devices (2 papers), Embedded Systems Design Techniques (1 paper), Stochastic Gradient Optimization Techniques (1 paper) and Neural Networks and Applications (1 paper). The work is most often cited by research in Hardware and Architecture (40 citations), Electrical and Electronic Engineering (233 citations) and Artificial Intelligence (69 citations). Ameya D. Patil has collaborated with scholars based in United States, Portugal and Germany. Frequent co-authors include Naresh R. Shanbhag, Mingu Kang, Sujan K. Gonugondla, Yongjune Kim, Haocheng Hua, Naveen Verma, Lav R. Varshney, Charbel Sakr, Sasikanth Manipatruni and Eric Pop. Their work appears in journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems I Regular Papers.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.