Aditya Japa

535 total citations
19 papers, 128 citations indexed

About

Aditya Japa is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computational Theory and Mathematics. According to data from OpenAlex, Aditya Japa has authored 19 papers receiving a total of 128 indexed citations (citations by other indexed papers that have themselves been cited), including 19 papers in Electrical and Electronic Engineering, 5 papers in Hardware and Architecture and 1 paper in Computational Theory and Mathematics. Recurrent topics in Aditya Japa's work include Advancements in Semiconductor Devices and Circuit Design (14 papers), Semiconductor materials and devices (13 papers) and Ferroelectric and Negative Capacitance Devices (9 papers). Aditya Japa is often cited by papers focused on Advancements in Semiconductor Devices and Circuit Design (14 papers), Semiconductor materials and devices (13 papers) and Ferroelectric and Negative Capacitance Devices (9 papers). Aditya Japa collaborates with scholars based in India, China and South Korea. Aditya Japa's co-authors include Ramesh Vaddi, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Siva Yellampalli, Brajesh Kumar Kaushik, K. Sri Rama Krishna, Jun Rim Choi, Santosh Kumar Vishvakarma, Vijay Rao Kumbhare and Chongyan Gu and has published in prestigious journals such as IEEE Circuits and Systems Magazine, International Journal of Circuit Theory and Applications and Journal of Computational Electronics.

In The Last Decade

Aditya Japa

19 papers receiving 118 citations

Peers

Aditya Japa
D. Mohapatra India
Pramod Kumar Patel India
Ming-Chien Tsai Taiwan
Ajay N. Bhoj United States
Adam Makosiej France
Satyanand Nalam United States
Rohit Lorenzo India
D. Hwang United States
D. Hoyniak United States
D. Mohapatra India
Aditya Japa
Citations per year, relative to Aditya Japa Aditya Japa (= 1×) peers D. Mohapatra

Countries citing papers authored by Aditya Japa

Since Specialization
Citations

This map shows the geographic impact of Aditya Japa's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Aditya Japa with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Aditya Japa more than expected).

Fields of papers citing papers by Aditya Japa

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Aditya Japa. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Aditya Japa. The network helps show where Aditya Japa may publish in the future.

Co-authorship network of co-authors of Aditya Japa

This figure shows the co-authorship network connecting the top 25 collaborators of Aditya Japa. A scholar is included among the top collaborators of Aditya Japa based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Aditya Japa. Aditya Japa is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

19 of 19 papers shown
1.
Japa, Aditya, et al.. (2024). Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices. Research Portal (Queen's University Belfast). 1–5. 1 indexed citations
2.
Japa, Aditya, et al.. (2024). A Novel Methodology for Processor based PUF in Approximate Computing. Research Portal (Queen's University Belfast). 1–5. 2 indexed citations
3.
Japa, Aditya, et al.. (2023). Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. Microelectronics Journal. 133. 105711–105711. 11 indexed citations
4.
Japa, Aditya, Jiliang Zhang, Weiqiang Liu, & Chongyan Gu. (2023). Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality?. 1–6. 3 indexed citations
5.
Japa, Aditya, Subhendu Kumar Sahoo, Ramesh Vaddi, & Manoj Kumar Majumder. (2022). Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption. Journal of Computational Electronics. 3 indexed citations
6.
Japa, Aditya, et al.. (2021). Negative capacitance FETs for energy efficient and hardware secure logic designs. Microelectronics Journal. 119. 105320–105320. 16 indexed citations
7.
Japa, Aditya, et al.. (2021). Steep Switching NCFET based Logic for Future Energy Efficient Electronics. 327–330. 7 indexed citations
8.
Japa, Aditya, Manoj Kumar Majumder, Subhendu Kumar Sahoo, & Ramesh Vaddi. (2021). Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things. International Journal of Circuit Theory and Applications. 49(8). 2299–2311. 3 indexed citations
9.
Japa, Aditya, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi, & Brajesh Kumar Kaushik. (2021). Hardware Security Exploiting Post-CMOS Devices: Fundamental Device Characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap. IEEE Circuits and Systems Magazine. 21(3). 4–30. 20 indexed citations
10.
Japa, Aditya, Manoj Kumar Majumder, Subhendu Kumar Sahoo, & Ramesh Vaddi. (2020). Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator. IET Circuits Devices & Systems. 14(5). 640–647. 6 indexed citations
11.
Majumder, Manoj Kumar, Vijay Rao Kumbhare, Aditya Japa, & Brajesh Kumar Kaushik. (2020). Introduction to Microelectronics to Nanoelectronics: Design and Technology. 1 indexed citations
12.
Japa, Aditya, Manoj Kumar Majumder, Subhendu Kumar Sahoo, & Ramesh Vaddi. (2020). Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage. International Journal of Circuit Theory and Applications. 48(4). 524–538. 7 indexed citations
13.
Majumder, Manoj Kumar, Vijay Rao Kumbhare, Aditya Japa, & Brajesh Kumar Kaushik. (2020). Introduction to Microelectronics to Nanoelectronics. 5 indexed citations
14.
Japa, Aditya, Manoj Kumar Majumder, Subhendu Kumar Sahoo, & Ramesh Vaddi. (2019). Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks. IET Circuits Devices & Systems. 13(5). 689–695. 8 indexed citations
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Japa, Aditya, et al.. (2016). Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. IET Circuits Devices & Systems. 10(6). 522–527. 13 indexed citations
19.
Japa, Aditya, et al.. (2014). Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm. 1–5. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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