Zuocheng Xing

626 total citations
54 papers, 442 citations indexed

About

Zuocheng Xing is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Hardware and Architecture. According to data from OpenAlex, Zuocheng Xing has authored 54 papers receiving a total of 442 indexed citations (citations by other indexed papers that have themselves been cited), including 35 papers in Electrical and Electronic Engineering, 28 papers in Computer Networks and Communications and 15 papers in Hardware and Architecture. Recurrent topics in Zuocheng Xing's work include Advanced Wireless Communication Techniques (16 papers), Parallel Computing and Optimization Techniques (12 papers) and Interconnection Networks and Systems (11 papers). Zuocheng Xing is often cited by papers focused on Advanced Wireless Communication Techniques (16 papers), Parallel Computing and Optimization Techniques (12 papers) and Interconnection Networks and Systems (11 papers). Zuocheng Xing collaborates with scholars based in China, Germany and Canada. Zuocheng Xing's co-authors include Cang Liu, Chuan Tang, Minxuan Zhang, Zhonghai Lu, Axel Jantsch, Chaochao Feng, Qinglin Wang, Yu Deng, Xuejun Yang and Ying Zhang and has published in prestigious journals such as IEEE Access, Sensors and Future Generation Computer Systems.

In The Last Decade

Zuocheng Xing

50 papers receiving 426 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Zuocheng Xing China	10	272	230	143	39	27	54	442
Kirti Gupta India	13	760 2.8×	63 0.3×	78 0.5×	21 0.5×	16 0.6×	96	832
Xueqian Zhao United States	10	223 0.8×	198 0.9×	160 1.1×	20 0.5×		36	356
Dibakar Saha India	9	71 0.3×	162 0.7×	95 0.7×	34 0.9×	3 0.1×	29	299
Ramachandran Vaidyanathan United States	12	94 0.3×	234 1.0×	115 0.8×	41 1.1×		75	393
Haifeng Qian United States	13	541 2.0×	70 0.3×	210 1.5×	39 1.0×		43	684
Kiyotaka Yamamura Japan	13	168 0.6×	37 0.2×	36 0.3×	40 1.0×	20 0.7×	74	429
Piers W. Lawrence Belgium	8	171 0.6×	140 0.6×	6 0.0×	20 0.5×	9 0.3×	15	307
James D. Teresco United States	7	57 0.2×	187 0.8×	156 1.1×	12 0.3×		25	399
Rob Van der Wijngaart United States	7	193 0.7×	327 1.4×	302 2.1×	17 0.4×		11	485
David Glasco United States	5	193 0.7×	289 1.3×	311 2.2×	73 1.9×		13	533

Countries citing papers authored by Zuocheng Xing

Since Specialization

Citations

This map shows the geographic impact of Zuocheng Xing's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Zuocheng Xing with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Zuocheng Xing more than expected).

Fields of papers citing papers by Zuocheng Xing

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Zuocheng Xing. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Zuocheng Xing. The network helps show where Zuocheng Xing may publish in the future.

Co-authorship network of co-authors of Zuocheng Xing

This figure shows the co-authorship network connecting the top 25 collaborators of Zuocheng Xing. A scholar is included among the top collaborators of Zuocheng Xing based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Zuocheng Xing. Zuocheng Xing is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Xing, Zuocheng, et al.. (2021). Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph. IEEE Access. 9. 28377–28392. 3 indexed citations

Wang, Qinglin, et al.. (2020). An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture. IEEE Access. 8. 68068–68082. 1 indexed citations

Wang, Qinglin, et al.. (2020). A Low-Latency Successive Cancellation Hybrid Decoder for Convolutional Polar Codes. 5105–5109. 1 indexed citations

Wang, Qinglin, et al.. (2019). Algorithm and Architecture for Path Metric Aided Bit-Flipping Decoding of Polar Codes. abs 1711 11093. 1–6. 6 indexed citations

Liu, Cang, et al.. (2019). An Improved Concatenation Scheme of BCH-Polar Codes With Low-Latency Decoding Architecture. IEEE Access. 7. 95867–95877. 2 indexed citations

Xing, Zuocheng, et al.. (2018). CWLP: coordinated warp scheduling and locality-protected cache allocation on GPUs. Frontiers of Information Technology & Electronic Engineering. 19(2). 206–220. 2 indexed citations

Tang, Chuan, et al.. (2018). Approximate iteration detection and precoding in massive MIMO. China Communications. 15(5). 183–196. 12 indexed citations

Xing, Zuocheng, et al.. (2017). Locality based warp scheduling in GPGPUs. Future Generation Computer Systems. 82. 520–527. 10 indexed citations

Liu, Cang, et al.. (2017). Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25(5). 1714–1724. 7 indexed citations

10.

Liu, Cang, et al.. (2016). A Novel Architecture to Eliminate Bottlenecks in a Parallel Tiled QRD Algorithm for Future MIMO Systems. IEEE Transactions on Circuits & Systems II Express Briefs. 64(1). 26–30. 8 indexed citations

11.

Wang, Qinglin, et al.. (2015). A GPU-based Fast Solution for Riesz Space Fractional Reaction-Diffusion Equation. 1. 317–323. 1 indexed citations

12.

Wang, Feng, et al.. (2015). Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating. International Journal of Electronics. 103(8). 1332–1348. 3 indexed citations

13.

Wang, Feng, et al.. (2014). Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip. 504–511. 4 indexed citations

14.

Chen, Xiaobao, et al.. (2013). Accurate calculation of quantum kinetic energy of single-electron transistor at room temperature. 993–996. 1 indexed citations

15.

Cheng, Yu, et al.. (2011). Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design. Journal of Computer Science and Technology. 26(3). 504–519. 5 indexed citations

16.

Cheng, Yu, Yongwen Wang, Zuocheng Xing, & Minxuan Zhang. (2011). Characterizing Time-Varying Behavior and Predictability of Cache AVF. 720–725. 3 indexed citations

17.

Wang, Jing, et al.. (2010). Practice on layout-level radiation hardened technologies for I/O cells. ns 37. V1–365. 1 indexed citations

18.

Huang, Ping, et al.. (2010). A brief survey on power gating design. 788–790. 6 indexed citations

19.

Xing, Zuocheng. (2009). Research on the Parallel Implementation of Genetic Algorithm on CUDA Platform. Computer Engineering and Science. 2 indexed citations

20.

Chi, Yaqing, et al.. (2008). Reconfigurable single-electron transistor logic gates. 294. 567–570. 3 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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