Yusuke Matsunaga

1.5k citations
90 papers · 993 indexed · h-index 17
Topics
VLSI and FPGA Design Techniques (24 papers)VLSI and Analog Circuit Testing (24 papers)Formal Methods in Verification (21 papers)

In The Last Decade

Yusuke Matsunaga

82 papers receiving 939 citations

Peers

Yusuke Matsunaga
Comparison fields: 5 of 93
  • Hardware and Architecture 431
  • Computational Theory and Mathematics 416
  • Electrical and Electronic Engineering 393
  • Software 182
  • Artificial Intelligence 135
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Countries citing papers authored by Yusuke Matsunaga

Since Specialization
Citations

This map shows the geographic impact of Yusuke Matsunaga's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yusuke Matsunaga with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yusuke Matsunaga more than expected).

Fields of papers citing papers by Yusuke Matsunaga

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yusuke Matsunaga. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yusuke Matsunaga. The network helps show where Yusuke Matsunaga may publish in the future.

Co-authorship network of co-authors of Yusuke Matsunaga

This figure shows the co-authorship network connecting the top 25 collaborators of Yusuke Matsunaga. A scholar is included among the top collaborators of Yusuke Matsunaga based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yusuke Matsunaga. Yusuke Matsunaga is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
#WorkIndexed citations
1 0
2 9
3 17
4 6
5 4
6
A minimum test pattern set generation for large circuits
1
7 2
8 1
9 10
10 6
11
An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States
0
12 10
13 23
14 7
15 71
16
An efficient algorithm finding simple disjoint decompositions using BDDs
1
17
A New Algorithm for Boolean Matching Utilizing Structural Information
9
18
MINT-An Exact Algorithm for Finding Minimum Test Set (Special Section on VLSI Design and CAD Algorithms)
11
19 138
20
co-LODEX: A Cooperative Expert System for Logic design.
2

About Yusuke Matsunaga

Yusuke Matsunaga is a scholar working on Hardware and Architecture, Software and Computational Theory and Mathematics, having authored 90 papers that have together received 993 indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (24 papers), VLSI and Analog Circuit Testing (24 papers) and Formal Methods in Verification (21 papers). The work is most often cited by research in Hardware and Architecture (431 citations), Software (182 citations) and Computational Theory and Mathematics (416 citations). Yusuke Matsunaga has collaborated with scholars based in Japan, United States and Netherlands. Frequent co-authors include Masahiro Fujita, Manabu Ishikawa, Hiroyuki Higuchi, Manae Harada, Shunsuke Koshio, Atsuhiko Matsunaga, Shin‐ichi Teshima, Atsushi Yoshida, Tomi Ohtsuki and Patrick C. McGeer. Their work appears in journals such as Journal of Clinical Oncology, Aquaculture and American Journal of Kidney Diseases.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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