Yuji Osaki

617 citations

22 papers · 494 indexed · h-index 8

Co-authors: Tetsuya Hirose Masahiro Numa Nobutaka Kuroki Kei Matsumoto Osamu Kobayashi Masanori Hashimoto Takao Onoye
Topics: Advancements in Semiconductor Devices and Circuit Design (18 papers)Analog and Mixed-Signal Circuit Design (18 papers)Low-power high-performance VLSI design (12 papers)
Cited by: Biomedical Engineering Electrical and Electronic Engineering Hardware and Architecture
Journals: IEEE Journal of Solid-State Circuits Japanese Journal of Applied Physics IEICE Transactions on Electronics
Partner nations: Japan

In The Last Decade

Yuji Osaki

22 papers receiving 478 citations

Peers

Countries citing papers authored by Yuji Osaki

Since Specialization

Citations

This map shows the geographic impact of Yuji Osaki's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yuji Osaki with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yuji Osaki more than expected).

Fields of papers citing papers by Yuji Osaki

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yuji Osaki. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yuji Osaki. The network helps show where Yuji Osaki may publish in the future.

Co-authorship network of co-authors of Yuji Osaki

This figure shows the co-authorship network connecting the top 25 collaborators of Yuji Osaki. A scholar is included among the top collaborators of Yuji Osaki based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yuji Osaki. Yuji Osaki is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit 2014 ·IEICE Transactions on Electronics ·(unknown),Tetsuya Hirose,Yuji Osaki,(unknown),Nobutaka Kuroki,Masahiro Numa	4
2	1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs 2013 ·IEEE Journal of Solid-State Circuits ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	222
3	A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation 2013 ·IEICE Electronics Express ·(unknown),Tetsuya Hirose,Yuji Osaki,Masanori Hashimoto,Takao Onoye	6
4	A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator 2012 ·(unknown),Tetsuya Hirose,Yuji Osaki,(unknown),Nobutaka Kuroki,Masahiro Numa	10
5	A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs 2012 ·IEEE Journal of Solid-State Circuits ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	95
6	A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs 2012 ·(unknown),Tetsuya Hirose,Yuji Osaki,Nobutaka Kuroki,Masahiro Numa,Osamu Kobayashi	11
7	A level shifter circuit design by using input/output voltage monitoring technique for ultra-low voltage digital CMOS LSIs 2011 ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	7
8	Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique 2011 ·IEICE Transactions on Electronics ·Yuji Osaki,Tetsuya Hirose,Kei Matsumoto,Nobutaka Kuroki,Masahiro Numa	1
9	Temperature-Compensated Nano-Ampere Current Reference Circuit with Subthreshold Metal–Oxide–Semiconductor Field-Effect Transistor Resistor Ladder 2011 ·Japanese Journal of Applied Physics ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	5
10	A 105-nW CMOS thermal sensor for power-aware applications 2011 ·(unknown),Tetsuya Hirose,Yuji Osaki,Nobutaka Kuroki,Masahiro Numa	1
11	A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs 2011 ·IEICE Electronics Express ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	5
12	High current efficiency sense amplifier using body-bias control for ultra-low-voltage SRAM 2011 ·(unknown),Tetsuya Hirose,Kei Matsumoto,Yuji Osaki,Nobutaka Kuroki,Masahiro Numa	4
13	Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit 2011 ·IEICE Transactions on Electronics ·Kei Matsumoto,Tetsuya Hirose,Yuji Osaki,Nobutaka Kuroki,Masahiro Numa	1
14	A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder 2011 ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	3
15	Temperature-Compensated Nano-Ampere Current Reference Circuit with Subthreshold Metal–Oxide–Semiconductor Field-Effect Transistor Resistor Ladder 2011 ·Japanese Journal of Applied Physics ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	6
16	Nano-ampere CMOS current reference with little temperature dependence using small offset voltage 2010 ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	8
17	A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities 2010 ·Tetsuya Hirose,Yuji Osaki,Nobutaka Kuroki,Masahiro Numa	81
18	Temperature Compensated Nano-Ampere CMOS Current Reference Circuit Using Small Offset Voltage 2010 ·Yuji Osaki,Tetsuya Hirose,Nobutaka Kuroki,Masahiro Numa	1
19	Switching-voltage detection and compensation circuits for ultra-low-voltage CMOS inverters 2009 ·Kei Matsumoto,Tetsuya Hirose,Yuji Osaki,Nobutaka Kuroki,Masahiro Numa	1
20	Delay-compensation techniques for ultra-low-power subthreshold CMOS digital LSIs 2009 ·Yuji Osaki,Tetsuya Hirose,Kei Matsumoto,Nobutaka Kuroki,Masahiro Numa	8

About Yuji Osaki

Yuji Osaki is a scholar working on Biomedical Engineering, Electrical and Electronic Engineering and Cellular and Molecular Neuroscience, having authored 22 papers that have together received 494 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (18 papers), Analog and Mixed-Signal Circuit Design (18 papers) and Low-power high-performance VLSI design (12 papers). The work is most often cited by research in Biomedical Engineering (387 citations), Electrical and Electronic Engineering (468 citations) and Hardware and Architecture (17 citations). Yuji Osaki has collaborated with scholars based in Japan. Frequent co-authors include Tetsuya Hirose, Masahiro Numa, Nobutaka Kuroki, Kei Matsumoto, Osamu Kobayashi, Masanori Hashimoto and Takao Onoye. Their work appears in journals such as IEEE Journal of Solid-State Circuits, Japanese Journal of Applied Physics and IEICE Transactions on Electronics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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