Yoji Kajitani
- Electrical and Electronic Engineering top 2%
- Hardware and Architecture top 0.5%
- Computer Networks and Communications top 2%
- Industrial and Manufacturing Engineering top 1%
- Computational Theory and Mathematics top 2%
- Co-authors
- Shigetoshi NakatakeKunihiro FujiyoshiHideyuki MurataHiroshi MurataKeishi SakanushiShuichi UenoAtsushi TakahashiHiroyuki Yamazaki
- Topics
- VLSI and FPGA Design Techniques (74 papers)VLSI and Analog Circuit Testing (34 papers)Interconnection Networks and Systems (21 papers)
- Cited by
- Hardware and ArchitectureComputer Graphics and Computer-Aided DesignIndustrial and Manufacturing Engineering
- Journals
- IEEE Transactions on Vehicular TechnologyIEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsTheoretical Computer Science
- Partner nations
- JapanUnited StatesChina
In The Last Decade
Yoji Kajitani
88 papers receiving 2.2k citations
Hit Papers
Peers
Comparison fields: 5 of 61
- Electrical and Electronic Engineering 1.8k
- Hardware and Architecture 1.1k
- Computer Networks and Communications 570
- Industrial and Manufacturing Engineering 389
- Computational Theory and Mathematics 300
Countries citing papers authored by Yoji Kajitani
This map shows the geographic impact of Yoji Kajitani's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yoji Kajitani with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yoji Kajitani more than expected).
Fields of papers citing papers by Yoji Kajitani
This network shows the impact of papers produced by Yoji Kajitani. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yoji Kajitani. The network helps show where Yoji Kajitani may publish in the future.
Co-authorship network of co-authors of Yoji Kajitani
This figure shows the co-authorship network connecting the top 25 collaborators of Yoji Kajitani. A scholar is included among the top collaborators of Yoji Kajitani based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yoji Kajitani. Yoji Kajitani is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | Escape Fitting between a Pair of Pin-Sets | 2 |
| 2 | 14 | |
| 3 | 12 | |
| 4 | An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm | 3 |
| 5 | 4 | |
| 6 | An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut | 1 |
| 7 | The 3D-Packing by Meta Data Structure and Packing Heuristics | 63 |
| 8 | Schedule-clock-tree routing for semi-synchronous circuits | 7 |
| 9 | Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan(Special Section on Discrete Mathematics and Its Applications) | 0 |
| 10 | Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan | 4 |
| 11 | 16 | |
| 12 | Cost-Radius Balanced Spanning/Steiner Trees | 3 |
| 13 | Clock-Routing Driven Layout Methodology for Semi-Synchronous Circuit Design | 2 |
| 14 | 172 | |
| 15 | Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two | 5 |
| 16 | Universal Graphs for Graphs with Bounded Path-Width | 3 |
| 17 | 3 | |
| 18 | A Note on Dual Trail Partition of a Plane Graph | 1 |
| 19 | 0 | |
| 20 | Subgraph reachability of marked graphs. | 2 |
About Yoji Kajitani
Yoji Kajitani is a scholar working on Hardware and Architecture, Computer Graphics and Computer-Aided Design and Industrial and Manufacturing Engineering, having authored 102 papers that have together received 2.3k indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (74 papers), VLSI and Analog Circuit Testing (34 papers) and Interconnection Networks and Systems (21 papers). The work is most often cited by research in Hardware and Architecture (1.1k citations), Computer Graphics and Computer-Aided Design (207 citations) and Industrial and Manufacturing Engineering (389 citations). Yoji Kajitani has collaborated with scholars based in Japan, United States and China. Frequent co-authors include Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hideyuki Murata, Hiroshi Murata, Keishi Sakanushi, Shuichi Ueno, Atsushi Takahashi, Hiroyuki Yamazaki, Xuliang Zhang and Dinesh P. Mehta. Their work appears in journals such as IEEE Transactions on Vehicular Technology, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Theoretical Computer Science.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.