Weixin Gai

548 total citations
58 papers, 380 citations indexed

About

Weixin Gai is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Weixin Gai has authored 58 papers receiving a total of 380 indexed citations (citations by other indexed papers that have themselves been cited), including 52 papers in Electrical and Electronic Engineering, 20 papers in Biomedical Engineering and 4 papers in Hardware and Architecture. Recurrent topics in Weixin Gai's work include Advancements in PLL and VCO Technologies (37 papers), Radio Frequency Integrated Circuit Design (21 papers) and Analog and Mixed-Signal Circuit Design (17 papers). Weixin Gai is often cited by papers focused on Advancements in PLL and VCO Technologies (37 papers), Radio Frequency Integrated Circuit Design (21 papers) and Analog and Mixed-Signal Circuit Design (17 papers). Weixin Gai collaborates with scholars based in China, United States and Japan. Weixin Gai's co-authors include Kai Sheng, Yiqun Liu, Yoichi Koyanagi, Xiaojin Luo, Jian Jiang, Hongyi Chen, Linqi Shi, Takeshi Horie, Li Yang and E. Seevinck and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Electronics Letters and IEEE Sensors Journal.

In The Last Decade

Weixin Gai

50 papers receiving 369 citations

Peers

Weixin Gai

EEE

BE

PS

HA

MB

Wenbo Liu China

K.C. Dyer United States

Christian Fobel Canada

Wenning Jiang China

Kelvin Yi-Tse Lai Taiwan

Mohammad Taherzadeh‐Sani Iran

D. Sinitsky United States

Muhammed Bolatkale Netherlands

Eric Soenen United States

J. O'Neill United States

Wenbo Liu China

Weixin Gai

278 ×0.9

EEE

280 ×2.0

BE

0 ×0.0

PS

19 ×0.5

HA

13 ×0.8

MB

Citations per year, relative to Weixin Gai Weixin Gai (= 1×) peers Wenbo Liu

Countries citing papers authored by Weixin Gai

Since Specialization

Citations

This map shows the geographic impact of Weixin Gai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Weixin Gai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Weixin Gai more than expected).

Fields of papers citing papers by Weixin Gai

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Weixin Gai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Weixin Gai. The network helps show where Weixin Gai may publish in the future.

Co-authorship network of co-authors of Weixin Gai

This figure shows the co-authorship network connecting the top 25 collaborators of Weixin Gai. A scholar is included among the top collaborators of Weixin Gai based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Weixin Gai. Weixin Gai is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

1.

Zhang, Boyang, et al.. (2024). A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET. 1–2.

2.

Wu, Guangdong, et al.. (2023). A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS. IEEE Journal of Solid-State Circuits. 59(1). 19–28. 3 indexed citations

3.

Wu, Guangdong, et al.. (2023). 6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. 112–114. 2 indexed citations

4.

Gai, Weixin, et al.. (2022). A Residue Amplifier with 85 dB DC Gain and 15 GHz Closed-Loop Bandwidth for 14-Bit 3GSPS Pipeline ADC. Circuits Systems and Signal Processing. 41(12). 6694–6708.

5.

Sheng, Kai, Weixin Gai, Boyang Zhang, et al.. (2022). A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS. 2022 IEEE International Solid- State Circuits Conference (ISSCC). 118–120. 21 indexed citations

6.

Gai, Weixin, et al.. (2021). A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer. 1–5. 2 indexed citations

7.

Gai, Weixin, et al.. (2021). An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology. 1–4.

8.

Gai, Weixin, et al.. (2021). Equal-slope baud-rate CDR algorithm with optimized eye opening. Microelectronics Journal. 114. 105138–105138. 1 indexed citations

9.

Zhang, Boyang, et al.. (2021). Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver. 2. 1–5. 1 indexed citations

10.

Gai, Weixin, et al.. (2019). Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs. 1–4. 1 indexed citations

11.

Luo, Xiaojin, et al.. (2019). Wearable Tape-Based Smart Biosensing Systems for Lactate and Glucose. IEEE Sensors Journal. 20(7). 3757–3765. 24 indexed citations

12.

Gai, Weixin, et al.. (2018). A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. 114–116. 38 indexed citations

13.

Shi, Linqi, et al.. (2018). A 108fs_rms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching. 1–5. 1 indexed citations

14.

Shi, Linqi, et al.. (2017). A novel digital loop filter with frequency error prediction for fast-locking bang-bang ADPLL. 1–2. 2 indexed citations

15.

Wang, Yuan, et al.. (2014). Teaching Practice in Circuits and Systems Courses at Peking University: A Curriculum and Pedagogical Perspective. IEEE Circuits and Systems Magazine. 14(3). 45–54. 1 indexed citations

16.

Gai, Weixin, et al.. (2009). A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. IEEE Journal of Solid-State Circuits. 44(12). 3547–3559. 57 indexed citations

17.

Gai, Weixin, et al.. (2009). A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. 188–189,189a. 5 indexed citations

18.

Gai, Weixin, et al.. (2005). Gain-phase Co-equalization for widely-used high-speed cables. 35. 194–197. 1 indexed citations

19.

Gotoh, Kaoru, Hirotaka Tamura, H. Takauchi, et al.. (2003). A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking. 180–181. 12 indexed citations

20.

Chen, Hongyi, et al.. (2003). A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 33(1-2). 191–197. 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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