Walter Stechele
About
In The Last Decade
Walter Stechele
134 papers receiving 1.1k citations
Peers
Comparison fields: 5 of 75
- Hardware and Architecture 437
- Electrical and Electronic Engineering 434
- Computer Vision and Pattern Recognition 378
- Computer Networks and Communications 233
- Artificial Intelligence 155
Countries citing papers authored by Walter Stechele
This map shows the geographic impact of Walter Stechele's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Walter Stechele with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Walter Stechele more than expected).
Fields of papers citing papers by Walter Stechele
This network shows the impact of papers produced by Walter Stechele. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Walter Stechele. The network helps show where Walter Stechele may publish in the future.
Co-authorship network of co-authors of Walter Stechele
This figure shows the co-authorship network connecting the top 25 collaborators of Walter Stechele. A scholar is included among the top collaborators of Walter Stechele based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Walter Stechele. Walter Stechele is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 0 | |
| 2 | 2 | |
| 3 | 3 | |
| 4 | 62 | |
| 5 | 39 | |
| 6 | 1 | |
| 7 | Resource-Aware Programming for Robotic Vision | 1 |
| 8 | Improving Efficiency of Embedded Multi-core Platforms with Scratchpad Memories | 1 |
| 9 | RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study | 1 |
| 10 | Self-reconfigurable Control Architecture for Complex Robots. | 2 |
| 11 | An evaluation on using GPU coprocessing for software radios on a low-cost platform | 2 |
| 12 | Partitioning and context switching for a reconfigurable FPGA-based DAB receiver | 3 |
| 13 | An Efficient DVB-T2 Decoding Accelerator by Time-Multiplexing FPGA Resources | 1 |
| 14 | Partial reconfiguration on FPGAs in practice — Tools and applications | 15 |
| 15 | 4 | |
| 16 | Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro. | 6 |
| 17 | Towards a Framework and a Design Methodology for Autonomous SoC. | 3 |
| 18 | Optimization potential of CMOS power by wire spacing | 0 |
| 19 | 2 | |
| 20 | 0 |
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.