Sung Dae Suk

925 total citations
26 papers, 735 citations indexed

About

Sung Dae Suk is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Materials Chemistry. According to data from OpenAlex, Sung Dae Suk has authored 26 papers receiving a total of 735 indexed citations (citations by other indexed papers that have themselves been cited), including 26 papers in Electrical and Electronic Engineering, 17 papers in Biomedical Engineering and 1 paper in Materials Chemistry. Recurrent topics in Sung Dae Suk's work include Semiconductor materials and devices (26 papers), Advancements in Semiconductor Devices and Circuit Design (26 papers) and Nanowire Synthesis and Applications (17 papers). Sung Dae Suk is often cited by papers focused on Semiconductor materials and devices (26 papers), Advancements in Semiconductor Devices and Circuit Design (26 papers) and Nanowire Synthesis and Applications (17 papers). Sung Dae Suk collaborates with scholars based in South Korea, United Kingdom and United States. Sung Dae Suk's co-authors include Kyoung Hwan Yeo, Dong‐Won Kim, Donggun Park, Ming Li, Yun Young Yeoh, Keun Hwi Cho, Byung-Il Ryu, Won-Seong Lee, Min-Sang Kim and Chang Woo Oh and has published in prestigious journals such as IEEE Electron Device Letters, IEEE Transactions on Nanotechnology and Symposium on VLSI Technology.

In The Last Decade

Sung Dae Suk

26 papers receiving 712 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Sung Dae Suk South Korea 13 718 378 54 53 11 26 735
Kyoung Hwan Yeo South Korea 16 782 1.1× 396 1.0× 61 1.1× 58 1.1× 11 1.0× 32 803
Byung-Il Ryu South Korea 10 574 0.8× 253 0.7× 44 0.8× 36 0.7× 12 1.1× 36 585
Jing Zhuge China 15 626 0.9× 258 0.7× 63 1.2× 35 0.7× 5 0.5× 36 662
Luca De Michielis Switzerland 16 822 1.1× 293 0.8× 50 0.9× 81 1.5× 3 0.3× 31 843
R. Yu Ireland 9 721 1.0× 243 0.6× 31 0.6× 55 1.0× 3 0.3× 21 732
D. K. Mohata United States 19 1.1k 1.6× 311 0.8× 58 1.1× 128 2.4× 6 0.5× 31 1.1k
R. Ritzenthaler Belgium 17 1.1k 1.5× 116 0.3× 83 1.5× 76 1.4× 10 0.9× 121 1.1k
K.F. Lee United States 7 1.0k 1.4× 219 0.6× 125 2.3× 66 1.2× 4 0.4× 17 1.0k
R. Rios United States 15 1.2k 1.7× 288 0.8× 51 0.9× 96 1.8× 8 0.7× 27 1.3k
Pramod Kumar Tiwari India 16 906 1.3× 219 0.6× 36 0.7× 24 0.5× 4 0.4× 105 934

Countries citing papers authored by Sung Dae Suk

Since Specialization
Citations

This map shows the geographic impact of Sung Dae Suk's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Sung Dae Suk with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Sung Dae Suk more than expected).

Fields of papers citing papers by Sung Dae Suk

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Sung Dae Suk. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Sung Dae Suk. The network helps show where Sung Dae Suk may publish in the future.

Co-authorship network of co-authors of Sung Dae Suk

This figure shows the co-authorship network connecting the top 25 collaborators of Sung Dae Suk. A scholar is included among the top collaborators of Sung Dae Suk based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Sung Dae Suk. Sung Dae Suk is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Kim, Dong‐Won, Ming Li, Kyoung Hwan Yeo, et al.. (2008). Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate. 117–118. 5 indexed citations
2.
Kim, Junsoo, Seungwon Yang, Jaehong Lee, et al.. (2008). Investigation of mobility in twin silicon nanowire MOSFETs (TSNWFETs). 50–52. 4 indexed citations
3.
Suk, Sung Dae, Kyoung Hwan Yeo, Keun Hwi Cho, et al.. (2008). High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer. IEEE Transactions on Nanotechnology. 7(2). 181–184. 43 indexed citations
4.
Suk, Sung Dae, Yun Young Yeoh, Ming Li, et al.. (2008). TSNWFET for SRAM cell application: Performance variation and process dependency. 38–39. 22 indexed citations
5.
Suk, Sung Dae, et al.. (2008). Extraction of voltage transfer characteristic of inverter based on TSNWFETs. 28. 43–45. 2 indexed citations
6.
Yeo, Kyoung Hwan, Keun Hwi Cho, Ming Li, et al.. (2008). Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory. 138–139. 16 indexed citations
7.
Cho, Keun Hwi, Sung Dae Suk, Yun Young Yeoh, et al.. (2007). Temperature-Dependent Characteristics of Cylindrical Gate-All-Around Twin Silicon Nanowire MOSFETs (TSNWFETs). IEEE Electron Device Letters. 28(12). 1129–1131. 18 indexed citations
8.
Suk, Sung Dae, Kyoung Hwan Yeo, Keun Hwi Cho, et al.. (2007). Gate-all-around Twin Silicon nanowire SONOS Memory. 45. 142–143. 25 indexed citations
9.
10.
Suk, Sung Dae, Ming Li, Yun Young Yeoh, et al.. (2007). Investigation of nanowire size dependency on TSNWFET. 891–894. 73 indexed citations
11.
Suk, Sung Dae, Sung‐Young Lee, Sungmin Kim, et al.. (2006). High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability. 717–720. 190 indexed citations
12.
Suk, Sung Dae, Kyoung Hwan Yeo, Keun Hwi Cho, et al.. (2006). High performance twin silicon nanowire MOSFET(TSNWFET) on bulk si wafer. 212–213. 1 indexed citations
13.
Li, Ming, Kyoung Hwan Yeo, Sung Dae Suk, et al.. (2006). Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate. Symposium on VLSI Technology. 94–95. 60 indexed citations
14.
Suk, Sung Dae, Ming Li, Yun Young Yeoh, et al.. (2006). Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure. 142–143. 12 indexed citations
15.
Yeo, Kyoung Hwan, Sung Dae Suk, Ming Li, et al.. (2006). Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires. 1–4. 153 indexed citations
16.
Hong, Ki‐Ha, Jongseob Kim, Sung‐Hoon Lee, et al.. (2006). Channel Engineering of Silicon Nanowire Field Effect Transistor: Non-Equilibrium Green's Function Study. 1281–1283. 2 indexed citations
17.
18.
Kim, Sungmin, Hye Jin Jo, Ming Li, et al.. (2005). A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm application. 639–642. 15 indexed citations
19.
Kim, Sung Min, Chang Woo Oh, Sung Dae Suk, et al.. (2005). Fully working high performance multi-channel field effect transistor (MCFET) SRAM cell on bulk Si substrate using TiN single metal gate. 196–197. 3 indexed citations
20.
Oh, Chang Woo, Sung Dae Suk, Yong Kyu Lee, et al.. (2005). Damascene gate FinFET SONOS memory implemented on bulk silicon wafer. 893–896. 25 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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2026