Srinivasan Murali

6.4k total citations · 3 hit papers
84 papers, 4.7k citations indexed

About

Srinivasan Murali is a scholar working on Computer Networks and Communications, Electrical and Electronic Engineering and Hardware and Architecture. According to data from OpenAlex, Srinivasan Murali has authored 84 papers receiving a total of 4.7k indexed citations (citations by other indexed papers that have themselves been cited), including 59 papers in Computer Networks and Communications, 41 papers in Electrical and Electronic Engineering and 38 papers in Hardware and Architecture. Recurrent topics in Srinivasan Murali's work include Interconnection Networks and Systems (58 papers), Parallel Computing and Optimization Techniques (27 papers) and Embedded Systems Design Techniques (23 papers). Srinivasan Murali is often cited by papers focused on Interconnection Networks and Systems (58 papers), Parallel Computing and Optimization Techniques (27 papers) and Embedded Systems Design Techniques (23 papers). Srinivasan Murali collaborates with scholars based in Switzerland, Italy and United States. Srinivasan Murali's co-authors include Giovanni De Micheli, Luca Benini, David Atienza, Antoine Jalabert, Ciprian Seiculescu, Federico Angiolini, Stergios Stergiou, Davide Bertozzi, Kees Goossens and Martijn Coenen and has published in prestigious journals such as Neurology, IEEE Transactions on Computers and IEEE Transactions on Parallel and Distributed Systems.

In The Last Decade

Srinivasan Murali

84 papers receiving 4.5k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Bandwidth-constrained mapping of cores onto NoC architectures

2004 498 citations Srinivasan Murali, Giovanni De Micheli Design, Automation, and Test in Europe profile →
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

2005 426 citations Davide Bertozzi, Antoine Jalabert et al. IEEE Transactions on Parallel and Distributed Systems profile →
Bandwidth-constrained mapping of cores onto NoC architectures

2004 389 citations Srinivasan Murali, Giovanni De Micheli Proceedings Design, Automation and Test in Europe Conference and Exhibition profile →

Peers

Countries citing papers authored by Srinivasan Murali

Since Specialization

Citations

This map shows the geographic impact of Srinivasan Murali's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Srinivasan Murali with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Srinivasan Murali more than expected).

Fields of papers citing papers by Srinivasan Murali

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Srinivasan Murali. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Srinivasan Murali. The network helps show where Srinivasan Murali may publish in the future.

Co-authorship network of co-authors of Srinivasan Murali

This figure shows the co-authorship network connecting the top 25 collaborators of Srinivasan Murali. A scholar is included among the top collaborators of Srinivasan Murali based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Srinivasan Murali. Srinivasan Murali is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Periscope: A Keystroke Inference Attack Using Human Coupled Electromagnetic Emanations 2021 ·Wenqiang Jin, Srinivasan Murali, (unknown), Ming Li	22
2	SmartCardia monitor and syncope in a young woman - a new diagnostic tool 2020 ·Cardiovascular Medicine ·(unknown), Francisco Rincon, (unknown), Srinivasan Murali, (unknown), Jean‐Jácques Goy, (unknown)	1
3	Cardiac Ambulatory Monitoring: New Wireless Device Validated Against Conventional Holter Monitoring in a Case Series 2020 ·Frontiers in Cardiovascular Medicine ·Srinivasan Murali, Nicolas Brugger, Francisco Rincon, (unknown), Stéphane Cook, Jean‐Jácques Goy	11
4	Heart Rate and Oxygen Saturation Monitoring With a New Wearable Wireless Device in the Intensive Care Unit: Pilot Comparison Trial 2020 ·Zurich Open Repository and Archive (University of Zurich) ·Srinivasan Murali, Francisco Rincon, Tiziano Cassina, Stéphane Cook, Jean‐Jácques Goy	9
5	Ultra-Low Power Estimation of Heart Rate Under Physical Activity Using a Wearable Photoplethysmographic System 2016 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·(unknown), Srinivasan Murali, Francisco Rincon, David Atienza	13
6	Design of ultra-low-power smart wearable systems 2015 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·(unknown), Francisco Rincon, Srinivasan Murali, David Atienza	6
7	A method to remove deadlocks in networks-on-chips with wormhole flow control 2010 ·Design, Automation, and Test in Europe ·Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	13
8	Design of networks on chips for 3D ICs 2010 ·Asia and South Pacific Design Automation Conference ·Srinivasan Murali, Luca Benini, Giovanni De Micheli	2
9	SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips 2009 ·Design, Automation, and Test in Europe ·Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	57
10	Synthesis of networks on chips for 3D systems on chips 2009 ·Asia and South Pacific Design Automation Conference ·Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli	57
11	Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems 2009 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Vincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto	17
12	Bringing NoCs to 65 nm 2007 ·IEEE Micro ·Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini	48
13	Temperature-aware processor frequency assignment for MPSoCs using convex optimization 2007 ·Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh K. Gupta, Stephen Boyd, Giovanni De Micheli	102
14	Reliability Support for On-Chip Memories Using Networks-on-Chip 2006 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli	21
15	A Methodology for Mapping Multiple Use-Cases onto Networks on Chips 2006 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Srinivasan Murali, Martijn Coenen, A. Rădulescu, Kees Goossens, Giovanni De Micheli	118
16	NoC synthesis flow for customized domain specific multiprocessor systems-on-chip breakdown → 2005 ·IEEE Transactions on Parallel and Distributed Systems ·Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, (unknown), Stergios Stergiou, Luca Benini, Giovanni De Micheli	426
17	Performance driven reliable link design for networks on chips 2005 ·(unknown), Srinivasan Murali, Giovanni De Micheli	20
18	Bandwidth-constrained mapping of cores onto NoC architectures breakdown → 2004 ·Design, Automation, and Test in Europe ·Srinivasan Murali, Giovanni De Micheli	498
19	×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip 2004 ·Design, Automation, and Test in Europe ·Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli	163
20	Bandwidth-constrained mapping of cores onto NoC architectures breakdown → 2004 ·Proceedings Design, Automation and Test in Europe Conference and Exhibition ·Srinivasan Murali, Giovanni De Micheli	389

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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