Sascha Uhrig

794 total citations
38 papers, 416 citations indexed

About

Sascha Uhrig is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering. According to data from OpenAlex, Sascha Uhrig has authored 38 papers receiving a total of 416 indexed citations (citations by other indexed papers that have themselves been cited), including 37 papers in Hardware and Architecture, 18 papers in Computer Networks and Communications and 4 papers in Electrical and Electronic Engineering. Recurrent topics in Sascha Uhrig's work include Parallel Computing and Optimization Techniques (30 papers), Real-Time Systems Scheduling (27 papers) and Embedded Systems Design Techniques (25 papers). Sascha Uhrig is often cited by papers focused on Parallel Computing and Optimization Techniques (30 papers), Real-Time Systems Scheduling (27 papers) and Embedded Systems Design Techniques (25 papers). Sascha Uhrig collaborates with scholars based in Germany, France and United States. Sascha Uhrig's co-authors include Theo Ungerer, Jörg Mische, Florian Kluge, Rolf Ernst, Selma Saidi, Benoît Dupont de Dinechin, Mike Gerdes, Henrik Theiling, Julian Wolf and Martin Schoeberl and has published in prestigious journals such as IEEE Micro, ACM Transactions on Embedded Computing Systems and Concurrency and Computation Practice and Experience.

In The Last Decade

Sascha Uhrig

35 papers receiving 383 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Sascha Uhrig Germany	11	375	167	62	32	25	38	416
Martin Streubühr Germany	8	282 0.8×	186 1.1×	69 1.1×	33 1.0×	25 1.0×	15	334
George Lima Brazil	9	266 0.7×	172 1.0×	57 0.9×	47 1.5×	39 1.6×	34	325
Pascal Sainrat France	11	463 1.2×	252 1.5×	66 1.1×	33 1.0×	15 0.6×	40	492
Selma Saidi Germany	9	190 0.5×	138 0.8×	53 0.9×	17 0.5×	23 0.9×	28	248
Iuliana Bacivarov Switzerland	13	443 1.2×	324 1.9×	101 1.6×	24 0.8×	15 0.6×	27	488
Christine Rochange France	10	427 1.1×	195 1.2×	37 0.6×	39 1.2×	27 1.1×	38	459
Hugues Cassé France	7	308 0.8×	144 0.9×	19 0.3×	41 1.3×	18 0.7×	24	332
Daniel Grund Germany	11	495 1.3×	252 1.5×	26 0.4×	56 1.8×	30 1.2×	19	537
Héctor Posadas Spain	12	309 0.8×	150 0.9×	32 0.5×	27 0.8×	51 2.0×	41	374
Martin Horauer Austria	9	149 0.4×	121 0.7×	85 1.4×	57 1.8×	23 0.9×	55	256

Countries citing papers authored by Sascha Uhrig

Since Specialization

Citations

This map shows the geographic impact of Sascha Uhrig's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Sascha Uhrig with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Sascha Uhrig more than expected).

Fields of papers citing papers by Sascha Uhrig

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Sascha Uhrig. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Sascha Uhrig. The network helps show where Sascha Uhrig may publish in the future.

Co-authorship network of co-authors of Sascha Uhrig

This figure shows the co-authorship network connecting the top 25 collaborators of Sascha Uhrig. A scholar is included among the top collaborators of Sascha Uhrig based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Sascha Uhrig. Sascha Uhrig is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Schneider, Daniel, et al.. (2019). Safety and Security Coengineering in Embedded Systems. Security and Communication Networks. 2019. 1–2. 1 indexed citations

Freitag, Johannes & Sascha Uhrig. (2017). Dynamic interference quantification for multicore processors. 55. 1–6. 1 indexed citations

Agrawal, Ankit, Gerhard Fohler, Johannes Freitag, et al.. (2017). Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study. DROPS (Schloss Dagstuhl – Leibniz Center for Informatics). 24 indexed citations

Agrawal, Ankit, Gerhard Fohler, Jan Nowotsch, Sascha Uhrig, & Michael Paulitsch. (2016). Poster Abstract: Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with Resource Contentions. 1–1. 2 indexed citations

Saidi, Selma, Rolf Ernst, Sascha Uhrig, Henrik Theiling, & Benoît Dupont de Dinechin. (2015). The shift to multicores in real-time and safety-critical systems. 220–229. 24 indexed citations

Saidi, Selma, Rolf Ernst, Sascha Uhrig, Henrik Theiling, & Benoît Dupont de Dinechin. (2015). The shift to multicores in real-time and safety-critical systems. 220–229. 30 indexed citations

Uhrig, Sascha, et al.. (2013). A real‐time capable coherent data cache for multicores. Concurrency and Computation Practice and Experience. 26(6). 1342–1354. 3 indexed citations

Rochange, Christine, et al.. (2013). Time‐Predictable Architectures. CERN Document Server (European Organization for Nuclear Research).

Paolieri, Marco, Jörg Mische, Mike Gerdes, et al.. (2013). A hard real-time capable multi-core SMT processor. ACM Transactions on Embedded Computing Systems. 12(3). 1–26. 15 indexed citations

10.

Uhrig, Sascha, et al.. (2013). Performance Evaluation of the Time Analysable On-Demand Coherent Cache. 1887–1892. 2 indexed citations

11.

Wolf, Julian, Bernhard Fechner, Sascha Uhrig, & Theo Ungerer. (2012). Fine-grained timing and control flow error checking for hard real-time task execution. OPUS (Augsburg University). 257–266. 4 indexed citations

12.

Uhrig, Sascha. (2011). Moving Execution — Motion. 28(1). 157–160. 1 indexed citations

13.

Wolf, Julian, Mike Gerdes, Florian Kluge, et al.. (2010). RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor. OPUS (Augsburg University). 193–201. 29 indexed citations

14.

Uhrig, Sascha, et al.. (2010). Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration. OPUS (Augsburg University). 71–79. 4 indexed citations

15.

Ungerer, Theo, Francisco J. Cazorla, Pascal Sainrat, et al.. (2010). Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. IEEE Micro. 30(5). 66–75. 108 indexed citations

16.

Mische, Jörg, Sascha Uhrig, Florian Kluge, & Theo Ungerer. (2010). Using SMT to Hide Context Switch Times of Large Real-Time Tasksets. OPUS (Augsburg University). 1 3 8. 255–264. 2 indexed citations

17.

Uhrig, Sascha, et al.. (2010). The Two-dimensional Superscalar GAP Processor Architecture. OPUS (Augsburg University). 3. 71–81. 6 indexed citations

18.

Uhrig, Sascha, et al.. (2008). Predictable dynamic instruction scratchpad for simultaneous multithreaded processors. OPUS (Augsburg University). 38–45. 22 indexed citations

19.

Uhrig, Sascha. (2008). A Flexible Java-on-Chip Solution Eine flexible Java-on-Chip Lösung. it - Information Technology. 50(5). 317–323. 1 indexed citations

20.

Brinkschulte, Uwe, Sascha Uhrig, & Theo Ungerer. (2005). Der mehrfädige Komodo-Mikrocontroller (The Multithreaded Komodo Microcontroller). it - Information Technology. 47(3). 117–122. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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