Rong-Jyi Yang

427 total citations
13 papers, 337 citations indexed

About

Rong-Jyi Yang is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Condensed Matter Physics. According to data from OpenAlex, Rong-Jyi Yang has authored 13 papers receiving a total of 337 indexed citations (citations by other indexed papers that have themselves been cited), including 13 papers in Electrical and Electronic Engineering, 11 papers in Biomedical Engineering and 1 paper in Condensed Matter Physics. Recurrent topics in Rong-Jyi Yang's work include Advancements in PLL and VCO Technologies (11 papers), Analog and Mixed-Signal Circuit Design (10 papers) and Radio Frequency Integrated Circuit Design (7 papers). Rong-Jyi Yang is often cited by papers focused on Advancements in PLL and VCO Technologies (11 papers), Analog and Mixed-Signal Circuit Design (10 papers) and Radio Frequency Integrated Circuit Design (7 papers). Rong-Jyi Yang collaborates with scholars based in Taiwan and China. Rong-Jyi Yang's co-authors include Shen-Iuan Liu, Shen-Iuan Liu, Chia-Yu Yao, Shangping Chen, Weicheng Chen, Wei‐Cheng Chen and Hsien‐Chin Chiu and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Rong-Jyi Yang

13 papers receiving 324 citations

Peers

Rong-Jyi Yang
Romesh Kumar Nandwana United States
Shengchang Cai United States
P. Vorenkamp Netherlands
Hiva Hedayati United States
Mitch Entezari United States
S. Rezeq United States
I. Elahi United States
Romesh Kumar Nandwana United States
Rong-Jyi Yang
Citations per year, relative to Rong-Jyi Yang Rong-Jyi Yang (= 1×) peers Romesh Kumar Nandwana

Countries citing papers authored by Rong-Jyi Yang

Since Specialization
Citations

This map shows the geographic impact of Rong-Jyi Yang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Rong-Jyi Yang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Rong-Jyi Yang more than expected).

Fields of papers citing papers by Rong-Jyi Yang

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Rong-Jyi Yang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Rong-Jyi Yang. The network helps show where Rong-Jyi Yang may publish in the future.

Co-authorship network of co-authors of Rong-Jyi Yang

This figure shows the co-authorship network connecting the top 25 collaborators of Rong-Jyi Yang. A scholar is included among the top collaborators of Rong-Jyi Yang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Rong-Jyi Yang. Rong-Jyi Yang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

13 of 13 papers shown
1.
Chen, Weicheng, et al.. (2015). A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24(1). 17–25. 21 indexed citations
2.
Yao, Chia-Yu, et al.. (2014). Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23(3). 567–574. 22 indexed citations
3.
Chen, Wei‐Cheng, et al.. (2012). A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm. 338–342. 3 indexed citations
4.
Yang, Rong-Jyi, et al.. (2009). Loop latency reduction technique for all-digital clock and data recovery circuits. 309–312. 6 indexed citations
5.
Yang, Rong-Jyi, et al.. (2008). An All-Digital Fast-Locking Programmable DLL-Based Clock Generator. IEEE Transactions on Circuits and Systems I Regular Papers. 55(1). 361–369. 23 indexed citations
6.
Chiu, Hsien‐Chin, et al.. (2007). A High Isolation 0.15¿m Depletion-Mode pHEMT SPDT Switch Using Field-Plate Technology. 52. 1–4. 3 indexed citations
7.
Chiu, Hsien‐Chin, et al.. (2007). A Compact Size Ka Band pHEMT MMIC Frequency Tripler with CPW Technology. 1–3. 1 indexed citations
8.
Yang, Rong-Jyi & Shen-Iuan Liu. (2007). A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 $\mu{\hbox {m}}$ CMOS Technology. IEEE Journal of Solid-State Circuits. 42(11). 2338–2347. 61 indexed citations
9.
Yang, Rong-Jyi & Shen-Iuan Liu. (2007). A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm. IEEE Journal of Solid-State Circuits. 42(2). 361–373. 118 indexed citations
10.
Yang, Rong-Jyi, et al.. (2006). A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit. IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications. 53(4). 842–847. 24 indexed citations
11.
Yang, Rong-Jyi, et al.. (2006). A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit. IEEE Journal of Solid-State Circuits. 41(6). 1380–1390. 15 indexed citations
12.
Yang, Rong-Jyi. (2005). A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs. IEICE Transactions on Electronics. E88-C(6). 1248–1252. 5 indexed citations
13.
Yang, Rong-Jyi, Shangping Chen, & Shen-Iuan Liu. (2004). A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet. IEEE Journal of Solid-State Circuits. 39(8). 1356–1360. 35 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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