Rajeev Murgai

1.4k total citations
55 papers, 754 citations indexed

About

Rajeev Murgai is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computational Theory and Mathematics. According to data from OpenAlex, Rajeev Murgai has authored 55 papers receiving a total of 754 indexed citations (citations by other indexed papers that have themselves been cited), including 44 papers in Electrical and Electronic Engineering, 38 papers in Hardware and Architecture and 14 papers in Computational Theory and Mathematics. Recurrent topics in Rajeev Murgai's work include Low-power high-performance VLSI design (41 papers), VLSI and FPGA Design Techniques (30 papers) and VLSI and Analog Circuit Testing (23 papers). Rajeev Murgai is often cited by papers focused on Low-power high-performance VLSI design (41 papers), VLSI and FPGA Design Techniques (30 papers) and VLSI and Analog Circuit Testing (23 papers). Rajeev Murgai collaborates with scholars based in United States, Japan and Brazil. Rajeev Murgai's co-authors include Alberto Sangiovanni‐Vincentelli, Robert K. Brayton, Narendra Shenoy, Gustavo Wilke, Masahiro Fujita, William W. Walker, Arlindo L. Oliveira, Masato Fujita, Jaijeet Roychowdhury and Peng He and has published in prestigious journals such as Proceedings of the IEEE, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Journal of Computational Electronics.

In The Last Decade

Rajeev Murgai

50 papers receiving 676 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Rajeev Murgai United States	14	595	585	228	93	37	55	754
A. Srinivasan United States	12	402 0.7×	280 0.5×	157 0.7×	79 0.8×	46 1.2×	23	543
Seh-Woong Jeong South Korea	12	214 0.4×	280 0.5×	139 0.6×	104 1.1×	40 1.1×	28	394
Kanupriya Gulati United States	11	285 0.5×	273 0.5×	74 0.3×	115 1.2×	36 1.0×	35	419
Charles F. Webb United States	7	375 0.6×	327 0.6×	101 0.4×	188 2.0×	52 1.4×	12	470
Paul H. Bardell United States	11	648 1.1×	620 1.1×	89 0.4×	26 0.3×	49 1.3×	19	755
R. Burch United States	8	504 0.8×	360 0.6×	44 0.2×	29 0.3×	38 1.0×	20	561
John Lillis United States	19	1.0k 1.7×	739 1.3×	38 0.2×	276 3.0×	18 0.5×	48	1.1k
Priyank Kalla United States	16	307 0.5×	372 0.6×	426 1.9×	47 0.5×	171 4.6×	63	660
C. A. Krygowski United States	9	358 0.6×	288 0.5×	129 0.6×	147 1.6×	38 1.0×	12	423
D. Hough United States	6	106 0.2×	202 0.3×	176 0.8×	49 0.5×	50 1.4×	7	295

Countries citing papers authored by Rajeev Murgai

Since Specialization

Citations

This map shows the geographic impact of Rajeev Murgai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Rajeev Murgai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Rajeev Murgai more than expected).

Fields of papers citing papers by Rajeev Murgai

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Rajeev Murgai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Rajeev Murgai. The network helps show where Rajeev Murgai may publish in the future.

Co-authorship network of co-authors of Rajeev Murgai

This figure shows the co-authorship network connecting the top 25 collaborators of Rajeev Murgai. A scholar is included among the top collaborators of Rajeev Murgai based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Rajeev Murgai. Rajeev Murgai is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Murgai, Rajeev. (2015). Technology-Dependent Logic Optimization. Proceedings of the IEEE. 103(11). 2004–2020. 4 indexed citations

Wilke, Gustavo & Rajeev Murgai. (2007). Design and Analysis of "Tree+Local Meshes" Clock Architecture. 5 indexed citations

Wilke, Gustavo, et al.. (2006). Clock Distribution Architectures: A Comparative Study. 85–91. 34 indexed citations

Murgai, Rajeev, et al.. (2005). ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24(1). 56–64. 3 indexed citations

Shibuya, Toshiyuki, et al.. (2004). PDL: a new physical synthesis methodology. e84 a. 348–354. 1 indexed citations

Li, Yinghua, et al.. (2004). Xtalkdelay: a crosstalk-aware timing analysis tool for chip-level designs. 208–215. 2 indexed citations

Oliveira, Arlindo L. & Rajeev Murgai. (2003). On the problem of gate assignment under different rise and fall delays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22(6). 807–814. 2 indexed citations

Chakraborty, Supratik & Rajeev Murgai. (2002). Layout-driven Timing Optimization by Generalized De Morgan Transform. Asia and South Pacific Design Automation Conference. 647–654.

Fujita, Masato & Rajeev Murgai. (2002). Delay estimation and optimization of logic circuits: a survey. 25–30. 8 indexed citations

10.

Murgai, Rajeev. (2002). Layout-driven area-constrained timing optimization by net buffering. 379–386. 7 indexed citations

11.

Murgai, Rajeev, Robert K. Brayton, & Alberto Sangiovanni‐Vincentelli. (2002). On clustering for minimum delay/ara. 37 indexed citations

12.

Murgai, Rajeev. (2000). Layout-driven area-constrained timing optimization by net buffering. International Conference on Computer Aided Design. 379–386. 9 indexed citations

13.

Murgai, Rajeev. (1999). Performance optimization under rise and fall parameters. International Conference on Computer Aided Design. 185–190. 9 indexed citations

14.

Murgai, Rajeev. (1999). On the global fanout optimization problem. International Conference on Computer Aided Design. 511–515. 13 indexed citations

15.

Aggarwal, Rajat, Rajeev Murgai, & Masahiro Fujita. (1997). Speeding up technology-independent timing optimization by network partitioning. International Conference on Computer Aided Design. 83–90. 2 indexed citations

16.

Murgai, Rajeev, Robert K. Brayton, & Alberto Sangiovanni‐Vincentelli. (1995). Decomposition of logic functions for minimum transition activity. 404–410. 17 indexed citations

17.

Murgai, Rajeev, Robert K. Brayton, & Alberto Sangiovanni‐Vincentelli. (1995). Logic Synthesis for Field-Programmable Gate Arrays. 38 indexed citations

18.

Murgai, Rajeev, Robert K. Brayton, & Alberto Sangiovanni‐Vincentelli. (1993). Cube-packing and two-level minimization. International Conference on Computer Aided Design. 115–122. 1 indexed citations

19.

Murgai, Rajeev, Robert K. Brayton, & Alberto Sangiovanni‐Vincentelli. (1993). Sequential synthesis for table look up programmable gate arrays. 224–229. 11 indexed citations

20.

Murgai, Rajeev, Robert K. Brayton, & Alberto Sangiovanni‐Vincentelli. (1992). An improved synthesis algorithm for multiplexor-based PGA's. Design Automation Conference. 380–386. 30 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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