P. Tirumalai

652 total citations
20 papers, 430 citations indexed

About

P. Tirumalai is a scholar working on Hardware and Architecture, Computer Networks and Communications and Artificial Intelligence. According to data from OpenAlex, P. Tirumalai has authored 20 papers receiving a total of 430 indexed citations (citations by other indexed papers that have themselves been cited), including 14 papers in Hardware and Architecture, 9 papers in Computer Networks and Communications and 7 papers in Artificial Intelligence. Recurrent topics in P. Tirumalai's work include Parallel Computing and Optimization Techniques (13 papers), Embedded Systems Design Techniques (8 papers) and Interconnection Networks and Systems (5 papers). P. Tirumalai is often cited by papers focused on Parallel Computing and Optimization Techniques (13 papers), Embedded Systems Design Techniques (8 papers) and Interconnection Networks and Systems (5 papers). P. Tirumalai collaborates with scholars based in United States. P. Tirumalai's co-authors include Michael Schlansker, B. Ramakrishna Rau, Jon T. Butler, Yonghong Song, M. Tremblay, Tin‐Fook Ngai, Meng Lee, Mohan Rajagopalan and Gerhard W. Dueck and has published in prestigious journals such as Blood, IEEE Transactions on Computers and ACM SIGPLAN Notices.

In The Last Decade

P. Tirumalai

20 papers receiving 387 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
P. Tirumalai United States 8 352 217 80 72 53 20 430
Ross A. Towle United States 5 458 1.3× 267 1.2× 56 0.7× 60 0.8× 64 1.2× 6 500
Stephen J. Allan United States 6 369 1.0× 237 1.1× 43 0.5× 40 0.6× 75 1.4× 8 422
Kent Wilken United States 11 339 1.0× 221 1.0× 58 0.7× 161 2.2× 96 1.8× 22 444
Stan Liao United States 12 505 1.4× 239 1.1× 93 1.2× 110 1.5× 120 2.3× 21 575
Yau-Tsun Steven Li United States 9 650 1.8× 248 1.1× 115 1.4× 41 0.6× 28 0.5× 9 684
Shail Aditya United States 13 412 1.2× 261 1.2× 37 0.5× 98 1.4× 90 1.7× 17 472
David W. L. Yen United States 5 358 1.0× 255 1.2× 30 0.4× 56 0.8× 37 0.7× 10 391
E. A. de Kock Netherlands 5 268 0.8× 217 1.0× 33 0.4× 29 0.4× 26 0.5× 8 313
Tokuzo Kiyohara Japan 6 536 1.5× 342 1.6× 25 0.3× 91 1.3× 90 1.7× 11 569
Grant Haab United States 6 617 1.8× 393 1.8× 37 0.5× 93 1.3× 98 1.8× 7 661

Countries citing papers authored by P. Tirumalai

Since Specialization
Citations

This map shows the geographic impact of P. Tirumalai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by P. Tirumalai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites P. Tirumalai more than expected).

Fields of papers citing papers by P. Tirumalai

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by P. Tirumalai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by P. Tirumalai. The network helps show where P. Tirumalai may publish in the future.

Co-authorship network of co-authors of P. Tirumalai

This figure shows the co-authorship network connecting the top 25 collaborators of P. Tirumalai. A scholar is included among the top collaborators of P. Tirumalai based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with P. Tirumalai. P. Tirumalai is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Rajagopalan, Mohan, et al.. (2005). Processor Aware Anticipatory Prefetching in Loops. 5. 106–106. 3 indexed citations
2.
Song, Yonghong, et al.. (2005). Design and implementation of a compiler framework for helper threading on multi-core processors. 99–109. 32 indexed citations
3.
Tirumalai, P. & Jon T. Butler. (2003). Prime and non-prime implicants in the minimization of multiple-valued logic functions. 272–279. 2 indexed citations
4.
Dueck, Gerhard W., et al.. (2003). Multiple-valued programmable logic array minimization by simulated annealing. 220. 66–74. 3 indexed citations
5.
Tirumalai, P., et al.. (2002). Parallel algorithms for minimizing multiple-valued programmable logic arrays. 287–295. 3 indexed citations
6.
Tirumalai, P., et al.. (2002). Software pipelining and superblock scheduling: compilation techniques for VLIW machines. 202–213. 5 indexed citations
7.
Tirumalai, P., et al.. (2002). UltraSPARC-II: the advancement of ultracomputing. 417–423. 7 indexed citations
8.
Tirumalai, P., et al.. (2002). Parallelization of loops with exits on pipelined architectures. 200–212. 17 indexed citations
9.
Tirumalai, P., et al.. (2002). UltraSPARC: compiling for maximum floating-point performance. 408–416. 2 indexed citations
10.
Tremblay, M. & P. Tirumalai. (1995). Partners in platform design. IEEE Spectrum. 32(4). 20–26. 7 indexed citations
11.
Rau, B. Ramakrishna, et al.. (1992). Register Allocation for Modulo Scheduled Loops: Strategies, Algorithms and Heuristics. Blood. 113(13). 3119–29. 7 indexed citations
12.
Rau, B. Ramakrishna, Michael Schlansker, & P. Tirumalai. (1992). Code Generation Schemas for Modulo Scheduled DO-Loops and WHILE-Loops. 6 indexed citations
13.
Rau, B. Ramakrishna, et al.. (1992). Register allocation for software pipelined loops. 283–299. 132 indexed citations
14.
Rau, B. Ramakrishna, Michael Schlansker, & P. Tirumalai. (1992). Code generation schema for modulo scheduled loops. ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter. 23(1-2). 158–169. 72 indexed citations
15.
Rau, B. Ramakrishna, et al.. (1992). Register allocation for software pipelined loops. ACM SIGPLAN Notices. 27(7). 283–299. 16 indexed citations
16.
Tirumalai, P., Meng Lee, & Michael Schlansker. (1991). Parallelization of WHILE loops on pipelined architectures. The Journal of Supercomputing. 5(2-3). 119–136. 7 indexed citations
17.
Tirumalai, P. & Jon T. Butler. (1991). Minimization algorithms for multiple-valued programmable logic arrays. IEEE Transactions on Computers. 40(2). 167–177. 28 indexed citations
18.
Tirumalai, P., et al.. (1990). Parallelization of loops with exits on pipelined architectures. Conference on High Performance Computing (Supercomputing). 200–212. 56 indexed citations
19.
Tirumalai, P.. (1989). Multiple-valued programmable logic arrays. 4 indexed citations
20.
Tirumalai, P. & Jon T. Butler. (1988). Analysis of minimization algorithms for multiple-valued programmable logic arrays. 226–236. 21 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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