M.J. Avedillo

1.2k citations

114 papers · 830 indexed · h-index 14

Impact in

Electrical and Electronic Engineering top 5%
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
Hardware and Architecture top 10%

Papers in ⓘ

Hardware and Architecture 14
Electrical and Electronic Engineering 100
- Advancements in Semiconductor Devices and Circuit Design 52
- Low-power high-performance VLSI design 43
- Semiconductor materials and devices 39
- Advanced Memory and Neural Computing 23
- Ferroelectric and Negative Capacitance Devices 12
- Integrated Circuits and Semiconductor Failure Analysis 9

Co-authors: José M. Quintana (36 shared papers)J.M. Quintana (45 shared papers)Juan Núñez (46 shared papers)Valeriu Beiu (2 shared papers)A. Rueda (11 shared papers)B. Linares-Barranco (12 shared papers)Manuel Jiménez (14 shared papers)J.L. Huertas (8 shared papers)
Journals: Electronics Letters (11 papers)IEEE Transactions on Nanotechnology (8 papers)Frontiers in Neuroscience (4 papers)IEEE Transactions on Electron Devices (2 papers)IEEE Transactions on Circuits and Systems I Regular Papers (2 papers)
Partner nations: Spain France Switzerland

In The Last Decade

M.J. Avedillo

108 papers receiving 799 citations

Peers

Countries citing papers authored by M.J. Avedillo

Since Specialization

Citations

This map shows the geographic impact of M.J. Avedillo's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M.J. Avedillo with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M.J. Avedillo more than expected).

Fields of papers citing papers by M.J. Avedillo

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M.J. Avedillo. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M.J. Avedillo. The network helps show where M.J. Avedillo may publish in the future.

Co-authors

The 25 scholars most cited alongside M.J. Avedillo, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with M.J. Avedillo Line = papers co-authored together M.J. Avedillo links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 114 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	VLSI implementations of threshold logic- a comprehensive survey IEEE Transactions on Neural Networks ·Valeriu Beiu, José M. Quintana, M.J. Avedillo	2003	172
2	Multi-threshold threshold logic circuit design using resonant tunnelling devices Electronics Letters ·M.J. Avedillo, J.M. Quintana, Héctor Pettenghi, Peter M. Kelly, C.J. Thompson	2003	43
3	How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase IEEE Transactions on Neural Networks and Learning Systems ·Aida Todri‐Sanial, Stefania Carapezzi, Corentin Delacour, Madeleine Abernot, Thierry Gil, Elisabetta Corti, Siegfried Karg, Juan Núñez, Manuel Jiménez, M.J. Avedillo, B. Linares-Barranco	2021	36
4	Low-power CMOS threshold-logic gate Electronics Letters ·M.J. Avedillo, J.M. Quintana, A. Rueda, E. Jiménez	1995	35
5	A CMOS-compatible oscillation-based VO2 Ising machine solver Nature Communications ·Olivier Maher, Manuel Jiménez, Corentin Delacour, Nele Harnack, Juan Núñez, M.J. Avedillo, B. Linares-Barranco, Aida Todri‐Sanial, Giacomo Indiveri, Siegfried Karg	2024	28
6	Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic Frontiers in Neuroscience ·Juan Núñez, M.J. Avedillo, Manuel Jiménez, José M. Quintana, Aida Todri‐Sanial, Elisabetta Corti, Siegfried Karg, B. Linares-Barranco	2021	27
7	Hardware Implementation of Differential Oscillatory Neural Networks Using VO 2-Based Oscillators and Memristor-Bridge Circuits Frontiers in Neuroscience ·Jafar Shamsi, M.J. Avedillo, B. Linares-Barranco, Teresa Serrano‐Gotarredona	2021	24
8	A practical floating-gate Muller-C element using vMOS threshold gates IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ·Esther Rodriguez–Villegas, Gloria Huertas, M.J. Avedillo, J.M. Quintana, A. Rueda	2001	23
9	Increased Logic Functionality of Clocked Series-Connected RTDS IEEE Transactions on Nanotechnology ·M.J. Avedillo, J.M. Quintana, H.P. Roldan	2006	18
10	A threshold logic synthesis tool for RTD circuits M.J. Avedillo, J.M. Quintana	2004	18
11	Using multi-threshold threshold gates in RTD-based logic design: A case study Microelectronics Journal ·Héctor Pettenghi, M.J. Avedillo, J.M. Quintana	2007	15
12	Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs IEEE Transactions on Nanotechnology ·Juan Núñez, M.J. Avedillo	2016	15
13	State merging and state splitting via state assignment: a new FSM synthesis algorithm IEE Proceedings - Computers and Digital Techniques ·M.J. Avedillo, J.M. Quintana, J.L. Huertas	1994	15
14	Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ·M.J. Avedillo, José M. Quintana, Héctor Pettenghi	2006	14
15	Analysis of frequency divider RTD circuits IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ·José M. Quintana, M.J. Avedillo	2005	12
16	Insights Into the Operation of Hyper-FET-Based Circuits IEEE Transactions on Electron Devices ·M.J. Avedillo, Juan Núñez	2017	10
17	Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas IEEE Transactions on Electron Devices ·Juan Núñez, M.J. Avedillo	2016	10
18	Synchronisation and chaos in a laser diode driven by a resonant tunnelling diode IET Optoelectronics ·Bruno Romeira, J. M. L. Figueiredo, Thomas J. Slight, L Wang, Edward Wasige, C. N. Ironside, J.M. Quintana, M.J. Avedillo	2008	10
19	Efficient realisation of MOS-NDR threshold logic gates Electronics Letters ·Juan Núñez, M.J. Avedillo, José M. Quintana	2009	10
20	Improved Nanopipelined RTD Adder Using Generalized Threshold Gates IEEE Transactions on Nanotechnology ·Héctor Pettenghi, M.J. Avedillo, José M. Quintana	2009	10

About M.J. Avedillo

M.J. Avedillo is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Artificial Intelligence, Computational Theory and Mathematics and Computer Networks and Communications, having authored 114 papers that have together received 830 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (52 papers), Low-power high-performance VLSI design (43 papers), Semiconductor materials and devices (39 papers), Advanced Memory and Neural Computing (23 papers), Neural Networks and Reservoir Computing (13 papers), Analog and Mixed-Signal Circuit Design (12 papers), Ferroelectric and Negative Capacitance Devices (12 papers) and Integrated Circuits and Semiconductor Failure Analysis (9 papers). The work is most often cited by research in Electrical and Electronic Engineering (717 citations), Hardware and Architecture (79 citations), Computational Theory and Mathematics (133 citations), Artificial Intelligence (200 citations) and Cognitive Neuroscience (64 citations). M.J. Avedillo has collaborated with scholars based in Spain, France and Switzerland. Frequent co-authors include José M. Quintana, J.M. Quintana, Juan Núñez, Valeriu Beiu, A. Rueda, B. Linares-Barranco, Manuel Jiménez, J.L. Huertas, Aida Todri‐Sanial and Siegfried Karg. Their work appears in journals such as Electronics Letters, IEEE Transactions on Nanotechnology, Frontiers in Neuroscience, IEEE Transactions on Electron Devices and IEEE Transactions on Circuits and Systems I Regular Papers.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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