M. Valencia

437 total citations
49 papers, 258 citations indexed

About

M. Valencia is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Artificial Intelligence. According to data from OpenAlex, M. Valencia has authored 49 papers receiving a total of 258 indexed citations (citations by other indexed papers that have themselves been cited), including 25 papers in Electrical and Electronic Engineering, 20 papers in Hardware and Architecture and 15 papers in Artificial Intelligence. Recurrent topics in M. Valencia's work include Low-power high-performance VLSI design (19 papers), Cryptographic Implementations and Security (10 papers) and Physical Unclonable Functions (PUFs) and Hardware Security (8 papers). M. Valencia is often cited by papers focused on Low-power high-performance VLSI design (19 papers), Cryptographic Implementations and Security (10 papers) and Physical Unclonable Functions (PUFs) and Hardware Security (8 papers). M. Valencia collaborates with scholars based in Spain, United States and Saudi Arabia. M. Valencia's co-authors include Antonio J. Acosta, J.L. Huertas, M.J. Bellido, A. Barriga, Jürgen Kosel, David Conchouso, Ian G. Foulds, Joaquín Salas, Alfonso Torres and Arpys Arevalo and has published in prestigious journals such as IEEE Access, Sensors and IEEE Journal of Solid-State Circuits.

In The Last Decade

M. Valencia

43 papers receiving 245 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
M. Valencia Spain	9	104	93	92	63	27	49	258
K. Torki France	10	133 1.3×	29 0.3×	74 0.8×	81 1.3×	30 1.1×	40	270
Mohammad Javad Dousti United States	10	189 1.8×	68 0.7×	208 2.3×	21 0.3×	19 0.7×	25	416
Debjit Pal United States	10	148 1.4×	88 0.9×	30 0.3×	18 0.3×	10 0.4×	48	291
Zuying Luo China	11	190 1.8×	46 0.5×	34 0.4×	48 0.8×	18 0.7×	51	287
Nor Zaidi Haron Malaysia	9	402 3.9×	76 0.8×	37 0.4×	10 0.2×	26 1.0×	37	463
Lucian Prodan Romania	10	89 0.9×	22 0.2×	111 1.2×	41 0.7×	22 0.8×	53	229
Minah Lee United States	7	198 1.9×	83 0.9×	41 0.4×	49 0.8×	22 0.8×	35	269
Thanh‐Ha Le France	7	27 0.3×	68 0.7×	98 1.1×	83 1.3×	32 1.2×	15	179
Mengshu Sun United States	8	161 1.5×	36 0.4×	95 1.0×	135 2.1×	12 0.4×	23	306
Mahmoud Tabandeh Iran	10	282 2.7×	101 1.1×	45 0.5×	52 0.8×	47 1.7×	33	402

Countries citing papers authored by M. Valencia

Since Specialization

Citations

This map shows the geographic impact of M. Valencia's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. Valencia with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. Valencia more than expected).

Fields of papers citing papers by M. Valencia

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. Valencia. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. Valencia. The network helps show where M. Valencia may publish in the future.

Co-authorship network of co-authors of M. Valencia

This figure shows the co-authorship network connecting the top 25 collaborators of M. Valencia. A scholar is included among the top collaborators of M. Valencia based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with M. Valencia. M. Valencia is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Valencia, M., et al.. (2022). ICs tester design and its effect on application in electronics laboratories. 1–4. 1 indexed citations

Valencia, M., et al.. (2021). Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. IEEE Access. 9. 168444–168454. 4 indexed citations

Valencia, M., et al.. (2020). An Academic Approach to FPGA Design Based on a Distance Meter Circuit. IEEE Revista Iberoamericana de Tecnologias del Aprendizaje. 15(3). 123–128. 1 indexed citations

Valencia, M., et al.. (2020). ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium. IEEE Transactions on Circuits & Systems II Express Briefs. 67(11). 2682–2686.

Valencia, M., et al.. (2020). Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. Sensors. 20(23). 6909–6909. 7 indexed citations

Valencia, M., et al.. (2018). Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. 94. 1–6. 1 indexed citations

Valencia, M., et al.. (2018). Distance measurement as a practical example of FPGA design. idUS (Universidad de Sevilla). 1–4. 2 indexed citations

Valencia, M., et al.. (2017). Robust 1D Modelling for Automotive HVAC Warmup Prediction Using DFSS Approach. SAE technical papers on CD-ROM/SAE technical paper series. 1. 5 indexed citations

Conchouso, David, et al.. (2013). Simulation of SU-8 Frequency-Driven Scratch Drive Actuators. King Abdullah University of Science and Technology Repository (King Abdullah University of Science and Technology). 803–808. 8 indexed citations

10.

Acosta, Antonio J., et al.. (2005). Selective Clock-Gating for Low-Power Synchronous Counters. Journal of Low Power Electronics. 1(1). 11–19. 2 indexed citations

11.

Bellido, M.J., M. Valencia, Antonio J. Acosta, et al.. (2002). A new faster method for calculating the resolution coefficient of CMOS latches: Design of an optimum latch. 1993 IEEE International Symposium on Circuits and Systems. 2019–2022.

12.

Acosta, Antonio J., A. Barriga, M. Valencia, M.J. Bellido, & J.L. Huertas. (2002). Modeling of real bistables in VHDL. idUS (Universidad de Sevilla). 460–465. 2 indexed citations

13.

Acosta, Antonio J., et al.. (2002). Selective Clock-Gating for Low Power/Low Noise Synchronous Counters. Lecture notes in computer science. 448–457. 1 indexed citations

14.

Bellido, M.J., et al.. (2001). Switching activity evaluation of CMOS digitalcircuits using logic timing simulation. Electronics Letters. 37(9). 555–557. 1 indexed citations

15.

Bellido, M.J., et al.. (1997). Delay degradation effect in submicronic CMOS inverters. 4 indexed citations

16.

Valencia, M., et al.. (1996). Sangre, sudor y vísceras: historia del cine gore. Dialnet (Universidad de la Rioja).

17.

Acosta, Antonio J., M.J. Bellido, M. Valencia, A. Barriga, & J.L. Huertas. (1993). Fully Digital Redundant Random Number Generator in CMOS Technology. European Solid-State Circuits Conference. 1. 198–201. 3 indexed citations

18.

Acosta, Antonio J., M. Valencia, A. Barriga, J.L. Huertas, & M.J. Bellido. (1992). Multiple-valued pads for binary chips. Electronics Letters. 28(8). 794–796. 1 indexed citations

19.

Bellido, M.J., Antonio J. Acosta, M. Valencia, A. Barriga, & J.L. Huertas. (1992). Simple binary random number generator. Electronics Letters. 28(7). 617–618. 23 indexed citations

20.

Valencia, M., et al.. (1991). Metastable operation in RS flip-flops. International Journal of Electronics. 70(6). 1073–1091. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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