M. H. Vasantha

745 total citations
56 papers, 505 citations indexed

About

M. H. Vasantha is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, M. H. Vasantha has authored 56 papers receiving a total of 505 indexed citations (citations by other indexed papers that have themselves been cited), including 47 papers in Electrical and Electronic Engineering, 21 papers in Biomedical Engineering and 11 papers in Hardware and Architecture. Recurrent topics in M. H. Vasantha's work include Low-power high-performance VLSI design (28 papers), Analog and Mixed-Signal Circuit Design (21 papers) and Advancements in Semiconductor Devices and Circuit Design (14 papers). M. H. Vasantha is often cited by papers focused on Low-power high-performance VLSI design (28 papers), Analog and Mixed-Signal Circuit Design (21 papers) and Advancements in Semiconductor Devices and Circuit Design (14 papers). M. H. Vasantha collaborates with scholars based in India, Italy and Malaysia. M. H. Vasantha's co-authors include Y. B. Nithin Kumar, B. Naresh Kumar Reddy, Dheeraj Sharma, Edoardo Bonizzoni, Ahish Shylendra, Trilochan Panigrahi, Anirban Chatterjee and Shivnarayan Patidar and has published in prestigious journals such as IEEE Access, IEEE Transactions on Electron Devices and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

M. H. Vasantha

48 papers receiving 458 citations

Peers

M. H. Vasantha

EEE

BE

HA

CTM

CNC

Y. B. Nithin Kumar India

Ing-Chao Lin Taiwan

Mohammad Saeed Ansari Canada

Ali-Akbar Ahmadi Iran

Shen-Iuan Liu Taiwan

Noor Mahammad Sk India

N. Tzartzanis United States

Hamid Reza Mahdiani Iran

G. K. Sharma India

Ruzica Jevtić Spain

Y. B. Nithin Kumar India

M. H. Vasantha

645 ×1.6

EEE

283 ×1.7

BE

129 ×1.1

HA

94 ×1.0

CTM

91 ×1.1

CNC

Citations per year, relative to M. H. Vasantha M. H. Vasantha (= 1×) peers Y. B. Nithin Kumar

Countries citing papers authored by M. H. Vasantha

Since Specialization

Citations

This map shows the geographic impact of M. H. Vasantha's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. H. Vasantha with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. H. Vasantha more than expected).

Fields of papers citing papers by M. H. Vasantha

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. H. Vasantha. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. H. Vasantha. The network helps show where M. H. Vasantha may publish in the future.

Co-authorship network of co-authors of M. H. Vasantha

This figure shows the co-authorship network connecting the top 25 collaborators of M. H. Vasantha. A scholar is included among the top collaborators of M. H. Vasantha based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with M. H. Vasantha. M. H. Vasantha is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

1.

Vasantha, M. H., et al.. (2023). Approximate Three-Operand Binary Adder for Error-Resilient Applications. 287–291. 1 indexed citations

2.

Vasantha, M. H., et al.. (2023). A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS. IEEE Transactions on Electron Devices. 71(2). 1054–1059. 4 indexed citations

3.

Kumar, Y. B. Nithin, et al.. (2021). Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access. 9. 108119–108130. 12 indexed citations

4.

Vasantha, M. H., et al.. (2021). Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm. 127–130. 4 indexed citations

5.

Vasantha, M. H., et al.. (2021). Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications. Integration. 81. 268–279. 9 indexed citations

6.

Kumar, Y. B. Nithin, et al.. (2021). A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. 1–5. 2 indexed citations

7.

Kumar, Y. B. Nithin, et al.. (2020). An Approximate Low-Power Lifting Scheme Using Reversible Logic. IEEE Access. 8. 183367–183377. 10 indexed citations

8.

Chatterjee, Anirban, et al.. (2020). A Wideband 12 Phase Ring Oscillator for 5G Applications. 885–888.

9.

Kumar, Y. B. Nithin, et al.. (2020). Reversible Logic Implementation of Image Denoising for Grayscale Images. 17. 138–141. 1 indexed citations

10.

Vasantha, M. H., et al.. (2020). $$\pm \, 0.5$$ V, 254 $$\upmu $$W Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit. Circuits Systems and Signal Processing. 40(5). 2114–2134. 1 indexed citations

11.

Kumar, Y. B. Nithin, et al.. (2019). An Asynchronous Analog to Digital Converter for Video Camera Applications. 175–180. 2 indexed citations

12.

Kumar, Y. B. Nithin, et al.. (2019). Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability. 627–631.

13.

Vasantha, M. H., et al.. (2018). A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. 214–219. 4 indexed citations

14.

Vasantha, M. H., et al.. (2018). Design of Approximate Dividers for Error Tolerant Applications. 496–499. 17 indexed citations

15.

Kumar, Y. B. Nithin, et al.. (2017). High Performance Sense Amplifier Based Flip Flop for Driver Applications. 129–132. 3 indexed citations

16.

Shylendra, Ahish, Dheeraj Sharma, M. H. Vasantha, & Y. B. Nithin Kumar. (2017). Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor. Superlattices and Microstructures. 103. 93–101. 10 indexed citations

17.

Shylendra, Ahish, Dheeraj Sharma, M. H. Vasantha, & Y. B. Nithin Kumar. (2016). Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field effect transistor. Superlattices and Microstructures. 94. 119–130. 15 indexed citations

18.

Shylendra, Ahish, et al.. (2016). Implementation of double-gate junctionless transistor and its circuit performance analysis. 278–283. 3 indexed citations

19.

Shylendra, Ahish, Y. B. Nithin Kumar, Dheeraj Sharma, & M. H. Vasantha. (2015). Design of high performance Multiply-Accumulate Computation unit. 915–918. 7 indexed citations

20.

Reddy, B. Naresh Kumar, M. H. Vasantha, Y. B. Nithin Kumar, & Dheeraj Sharma. (2015). Communication energy constrained spare core on NoC. 1–4. 24 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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