Ahish Shylendra

502 total citations
23 papers, 377 citations indexed

About

Ahish Shylendra is a scholar working on Electrical and Electronic Engineering, Artificial Intelligence and Hardware and Architecture. According to data from OpenAlex, Ahish Shylendra has authored 23 papers receiving a total of 377 indexed citations (citations by other indexed papers that have themselves been cited), including 18 papers in Electrical and Electronic Engineering, 6 papers in Artificial Intelligence and 5 papers in Hardware and Architecture. Recurrent topics in Ahish Shylendra's work include Advancements in Semiconductor Devices and Circuit Design (9 papers), Advanced Memory and Neural Computing (7 papers) and Semiconductor materials and devices (7 papers). Ahish Shylendra is often cited by papers focused on Advancements in Semiconductor Devices and Circuit Design (9 papers), Advanced Memory and Neural Computing (7 papers) and Semiconductor materials and devices (7 papers). Ahish Shylendra collaborates with scholars based in United States and India. Ahish Shylendra's co-authors include Y. B. Nithin Kumar, Dheeraj Sharma, Amit Ranjan Trivedi, William A. Gaviria Rojas, Vinod K. Sangwan, Silu Guo, Hadallia Bergeron, Mark C. Hersam, M. H. Vasantha and Megan E. Beck and has published in prestigious journals such as Nature Communications, Nano Letters and IEEE Access.

In The Last Decade

Ahish Shylendra

23 papers receiving 368 citations

Peers

Countries citing papers authored by Ahish Shylendra

Since Specialization

Citations

This map shows the geographic impact of Ahish Shylendra's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ahish Shylendra with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ahish Shylendra more than expected).

Fields of papers citing papers by Ahish Shylendra

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ahish Shylendra. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ahish Shylendra. The network helps show where Ahish Shylendra may publish in the future.

Co-authorship network of co-authors of Ahish Shylendra

This figure shows the co-authorship network connecting the top 25 collaborators of Ahish Shylendra. A scholar is included among the top collaborators of Ahish Shylendra based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ahish Shylendra. Ahish Shylendra is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work	Indexed citations
1	Unifying Intrinsically-Operated Physically Unclonable Function and Random Number Generation in Analog Circuits: A Case Study on Successive Approximation ADC 2023 ·Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi	1
2	ENOS: Energy-Aware Network Operator Search in Deep Neural Networks 2022 ·IEEE Access ·(unknown), Ahish Shylendra, (unknown), Theja Tulabandhula, Wilfred Gomes, Ankush Chakrabarty, Amit Ranjan Trivedi	11
3	Higher order neural processing with input-adaptive dynamic weights on MoS2 memtransistor crossbars 2022 ·(unknown), Ahish Shylendra, (unknown), (unknown), Vinod K. Sangwan, Mark C. Hersam, Amit Ranjan Trivedi	6
4	Advanced Electrochemical Reamer (EC-Reamer) for Root Canal Treatment 2022 ·European Endodontic Journal ·(unknown), Wei Li, (unknown), Ahish Shylendra, Amit Ranjan Trivedi, Qian Xie, Christine D. Wu, Mathew T. Mathew	1
5	A Simulation Study on Minimizing Threshold Voltage Variability by Optimizing Oxygen Vacancy Concentration Under Metal Gate Granularity 2020 ·IEEE Electron Device Letters ·(unknown), Ahish Shylendra, D.J. Frank, Takashi Ando, Amit Ranjan Trivedi	1
6	Spiking neurons from tunable Gaussian heterojunction transistors 2020 ·Nature Communications ·Megan E. Beck, Ahish Shylendra, Vinod K. Sangwan, Silu Guo, William A. Gaviria Rojas, Hocheon Yoo, Hadallia Bergeron, K. Y. L. Su, Amit Ranjan Trivedi, Mark C. Hersam	86
7	MC²RAM: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference 2020 ·(unknown), Ahish Shylendra, Theja Tulabandhula, Amit Ranjan Trivedi	21
8	Non-parametric Statistical Density Function Synthesizer and Monte Carlo Sampler in CMOS 2020 ·Ahish Shylendra, (unknown), (unknown), Amit Ranjan Trivedi	1
9	An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors 2019 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi	4
10	Ultralow power acoustic feature-scoring using gaussian I-V transistors 2018 ·Amit Ranjan Trivedi, Ahish Shylendra	1
11	Ultralow Power Acoustic Feature-Scoring using Gaussian I-V Transistors 2018 ·Amit Ranjan Trivedi, Ahish Shylendra	3
12	Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor 2017 ·Superlattices and Microstructures ·Ahish Shylendra, Dheeraj Sharma, M. H. Vasantha, Y. B. Nithin Kumar	10
13	Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field effect transistor 2016 ·Superlattices and Microstructures ·Ahish Shylendra, Dheeraj Sharma, M. H. Vasantha, Y. B. Nithin Kumar	15
14	Implementation of double-gate junctionless transistor and its circuit performance analysis 2016 ·(unknown), (unknown), Ahish Shylendra, Dheeraj Sharma, M. H. Vasantha, Y. B. Nithin Kumar	3
15	Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor 2016 ·Ahish Shylendra, Dheeraj Sharma, M. H. Vasantha, Y. B. Nithin Kumar	10
16	DC and analogue/radio frequency performance optimisation of heterojunction double‐gate tunnel field‐effect transistor 2016 ·Micro & Nano Letters ·Ahish Shylendra, Dheeraj Sharma, Y. B. Nithin Kumar, (unknown)	4
17	Performance analysis of a novel hetero-junction tunnel FET based SRAM at 0.3V supply voltage 2016 ·(unknown), Ahish Shylendra, Dheeraj Sharma, M. H. Vasantha, Y. B. Nithin Kumar	1
18	Design of high performance Multiply-Accumulate Computation unit 2015 ·Ahish Shylendra, Y. B. Nithin Kumar, Dheeraj Sharma, M. H. Vasantha	7
19	Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping 2015 ·IEEE Transactions on Electron Devices ·Ahish Shylendra, Dheeraj Sharma, Y. B. Nithin Kumar, (unknown)	125
20	FPGA Implementation of Optimized Heterogeneous Adder for DSP Applications 2014 ·Ahish Shylendra, (unknown), (unknown), (unknown)	1

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact