Joseph Kozhaya

673 total citations
20 papers, 531 citations indexed

About

Joseph Kozhaya is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Control and Systems Engineering. According to data from OpenAlex, Joseph Kozhaya has authored 20 papers receiving a total of 531 indexed citations (citations by other indexed papers that have themselves been cited), including 19 papers in Electrical and Electronic Engineering, 12 papers in Hardware and Architecture and 3 papers in Control and Systems Engineering. Recurrent topics in Joseph Kozhaya's work include Low-power high-performance VLSI design (15 papers), Parallel Computing and Optimization Techniques (8 papers) and VLSI and FPGA Design Techniques (6 papers). Joseph Kozhaya is often cited by papers focused on Low-power high-performance VLSI design (15 papers), Parallel Computing and Optimization Techniques (8 papers) and VLSI and FPGA Design Techniques (6 papers). Joseph Kozhaya collaborates with scholars based in United States and Canada. Joseph Kozhaya's co-authors include Sani Nassif, Farid N. Najm, Malgorzata Marek-Sadowska, Aida Todri‐Sanial, Haifeng Qian, P.J. Restle, Ciaran J. Brennan, Sachin S. Sapatnekar, Joseph S. Palumbo and Cliff Sze and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and Journal of Electrostatics.

In The Last Decade

Joseph Kozhaya

20 papers receiving 505 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Joseph Kozhaya United States	11	485	202	65	56	36	20	531
Rajendran Panda United States	16	1.0k 2.1×	469 2.3×	50 0.8×	59 1.1×	30 0.8×	40	1.1k
Ronald A. Rohrer United States	11	381 0.8×	117 0.6×	39 0.6×	21 0.4×	33 0.9×	21	452
S.G. Walker United States	7	792 1.6×	535 2.6×	43 0.7×	40 0.7×	34 0.9×	9	853
G. Katopis United States	15	965 2.0×	158 0.8×	23 0.4×	74 1.3×	23 0.6×	63	1.0k
Ken Kundert United States	11	440 0.9×	133 0.7×	57 0.9×	32 0.6×	27 0.8×	26	513
Xueqian Zhao United States	10	223 0.5×	160 0.8×	52 0.8×	198 3.5×	17 0.5×	36	356
Chung-Kuan Cheng United States	12	504 1.0×	247 1.2×	26 0.4×	125 2.2×	5 0.1×	32	552
R. Telichevesky United States	6	325 0.7×	38 0.2×	83 1.3×	14 0.3×	50 1.4×	8	382
Bruce McGaughy United States	11	260 0.5×	102 0.5×	11 0.2×	52 0.9×	11 0.3×	23	385
Wayne Dai United States	9	460 0.9×	170 0.8×	23 0.4×	35 0.6×	45 1.3×	31	478

Countries citing papers authored by Joseph Kozhaya

Since Specialization

Citations

This map shows the geographic impact of Joseph Kozhaya's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Joseph Kozhaya with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Joseph Kozhaya more than expected).

Fields of papers citing papers by Joseph Kozhaya

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Joseph Kozhaya. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Joseph Kozhaya. The network helps show where Joseph Kozhaya may publish in the future.

Co-authorship network of co-authors of Joseph Kozhaya

This figure shows the co-authorship network connecting the top 25 collaborators of Joseph Kozhaya. A scholar is included among the top collaborators of Joseph Kozhaya based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Joseph Kozhaya. Joseph Kozhaya is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Restle, P.J., Joseph S. Palumbo, Joseph Kozhaya, et al.. (2014). PACMAN. 1–5. 5 indexed citations

Qian, Haifeng, et al.. (2012). Subtractive Router for Tree-Driven-Grid Clocks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31(6). 868–877. 8 indexed citations

Kozhaya, Joseph, P.J. Restle, & Haifeng Qian. (2011). Myth busters: microprocessor clocking is from Mars, ASICs clocking is from Venus. International Conference on Computer Aided Design. 271–275. 3 indexed citations

Kozhaya, Joseph, P.J. Restle, & Haifeng Qian. (2011). Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. 271–275. 4 indexed citations

Todri‐Sanial, Aida, Malgorzata Marek-Sadowska, & Joseph Kozhaya. (2008). Power supply noise aware workload assignment for multi-core systems. HAL (Le Centre pour la Communication Scientifique Directe). 330–337. 11 indexed citations

Todri‐Sanial, Aida, Malgorzata Marek-Sadowska, & Joseph Kozhaya. (2008). Power supply noise aware workload assignment for multi-core systems. 330–337. 13 indexed citations

Deutsch, A., et al.. (2007). Effect of noise on timing or data-pattern dependent delay variation when transmission-line effects are taken into account for on-chip wiring. 7–10. 5 indexed citations

Qian, Haifeng, Joseph Kozhaya, Sani Nassif, & Sachin S. Sapatnekar. (2005). A chip-level electrostatic discharge simulation strategy. 22. 315–318. 7 indexed citations

Brennan, Ciaran J., et al.. (2005). ESD design automation & methodology to prevent CDM failures in 130 & 90nm ASIC design systems. Journal of Electrostatics. 64(2). 112–127. 2 indexed citations

10.

Brennan, Ciaran J., et al.. (2004). ESD design automation for a 90nm ASIC design system. 1–8. 12 indexed citations

11.

Kozhaya, Joseph, et al.. (2004). An electrically robust method for placing power gating switches in voltage islands. 19. 321–324. 13 indexed citations

12.

Brennan, Ciaran J., et al.. (2004). Power network analysis for ESD robustness in a 90nm ASIC design system. 247–250. 2 indexed citations

13.

Kozhaya, Joseph, Sani Nassif, & Farid N. Najm. (2002). I/O buffer placement methodology for ASICs. 1. 245–248. 11 indexed citations

14.

Nassif, Sani & Joseph Kozhaya. (2002). Multi-grid methods for power grid simulation. 5. 457–460. 4 indexed citations

15.

Kozhaya, Joseph, Sani Nassif, & Farid N. Najm. (2002). Multigrid-like technique for power grid analysis. 480–487. 22 indexed citations

16.

Kozhaya, Joseph, Sani Nassif, & Farid N. Najm. (2002). A multigrid-like technique for power grid analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21(10). 1148–1160. 199 indexed citations

17.

Kozhaya, Joseph, Sani Nassif, & Farid N. Najm. (2001). Multigrid-like technique for power grid analysis. International Conference on Computer Aided Design. 480–487. 25 indexed citations

18.

Kozhaya, Joseph & Farid N. Najm. (2001). Power estimation for large sequential circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9(2). 400–407. 23 indexed citations

19.

Nassif, Sani & Joseph Kozhaya. (2000). Fast power grid simulation. 156–161. 142 indexed citations

20.

Kozhaya, Joseph & Farid N. Najm. (1997). Accurate power estimation for large sequential circuits. International Conference on Computer Aided Design. 488–493. 20 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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