Jiafeng Xie

1.0k citations

69 papers · 683 indexed · h-index 16

Artificial Intelligence top 2%
- Coding theory and cryptography 49
- Cryptography and Data Security 35
- Cryptographic Implementations and Security 20
- Quantum Computing Algorithms and Architecture 7
Information Systems top 2%
- Cryptography and Residue Arithmetic 39
Hardware and Architecture top 10%
- Physical Unclonable Functions (PUFs) and Hardware Security 4
Computational Theory and Mathematics top 5%
- Numerical Methods and Algorithms 3
Signal Processing top 10%
Electrical and Electronic Engineering
- Low-power high-performance VLSI design 3

Co-authors: Chiou‐Yng Lee Pramod Kumar Meher Anissa Sghaier Medien Zeghid Jeng‐Shyang Pan Zhi‐Hong Mao Ujjwal Guin Mehran Mozaffari Kermani
Cited by: Artificial Intelligence Information Systems Hardware and Architecture
Journals: IEEE Access (2 papers)IEEE Transactions on Computers (1 paper)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1 paper)
Partner nations: United States China Taiwan

In The Last Decade

Jiafeng Xie

63 papers receiving 661 citations

Peers

Countries citing papers authored by Jiafeng Xie

Since Specialization

Citations

This map shows the geographic impact of Jiafeng Xie's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jiafeng Xie with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jiafeng Xie more than expected).

Fields of papers citing papers by Jiafeng Xie

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jiafeng Xie. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jiafeng Xie. The network helps show where Jiafeng Xie may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Jiafeng Xie, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Jiafeng Xie Line = papers co-authored together Jiafeng Xie links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	EMINEM: Efficient FPGA Implementation of Mixed-RadIx NTT Hardware AccElerators for NIST Post-QuantuM Cryptography F alcon , Dilithium, and HAWK ACM Transactions on Reconfigurable Technology and Systems ·Yazheng Tu,Jiafeng Xie	2025	0
2	High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Pengzhou He,Tianyou Bao,Jiafeng Xie	2025	1
3	Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief IEEE Transactions on Circuits & Systems II Express Briefs ·Jiafeng Xie,Wenfeng Zhao,Hanho Lee,Debapriya Basu Roy,Xinmiao Zhang	2024	16
4	LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENC Pengzhou He,Ben Mongirdas,Çetin Kaya Koç,Jiafeng Xie	2024	1
5	LTE: Lightweight and Time-Efficient Hardware Encoder for Post-Quantum Scheme HQC IEEE Computer Architecture Letters ·Yazheng Tu,Pengzhou He,Chip-Hong Chang,Jiafeng Xie	2024	0
6	SCOPE: Schoolbook-Originated Novel Polynomial Multiplication Accelerators for NTRU-Based PQC IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Yazheng Tu,Shi Bai,Jinjun Xiong,Jiafeng Xie	2024	1
7	COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Pengzhou He,Yazheng Tu,Tianyou Bao,Leonel Sousa,Jiafeng Xie	2023	2
8	AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC ACM Transactions on Reconfigurable Technology and Systems ·Tianyou Bao,Pengzhou He,Jiafeng Xie,H S. Jacinto	2023	1
9	LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC Pengzhou He,Yazheng Tu,Jiafeng Xie	2023	4
10	Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography IEEE Transactions on Circuits and Systems I Regular Papers ·José Luis Imaña,Pengzhou He,Tianyou Bao,Yazheng Tu,Jiafeng Xie	2022	19
11	MiR-367 alleviates inflammatory injury of microglia by promoting M2 polarization via targeting CEBPA In Vitro Cellular & Developmental Biology - Animal ·Hui Pei,Qian Peng,Shewei Guo,Yulei Gu,Tongwen Sun,Xu D,Yumin Jiang,Jiafeng Xie,Luanluan Zhang,Zhiqiang Zhu	2020	12
12	Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Jiafeng Xie,Chiou‐Yng Lee,Pramod Kumar Meher,Zhi‐Hong Mao	2019	14
13	Tat expression led to increased histone 3 tri-methylation at lysine 27 and contributed to HIV latency in astrocytes through regulation of MeCP2 and Ezh2 expression Journal of NeuroVirology ·Ying Liu,Yinghua Niu,Lu Li,Khalid Amine Timani,Victor L. He,Chris Sanburns,Jiafeng Xie,Johnny J. He	2019	6
14	High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2^m) based on MSPB Chiou‐Yng Lee,Jiafeng Xie	2019	5
15	LSM Jiafeng Xie,Chiou‐Yng Lee	2019	1
16	Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials Jiafeng Xie,Pramod Kumar Meher,Xiaojun Zhou,Chiou‐Yng Lee	2018	8
17	Improving Fast Segmentation With Teacher-student Learning British Machine Vision Conference ·Jiafeng Xie,Bing Shuai,Jian–Fang Hu,Jingyang Lin,Wei‐Shi Zheng	2018	4
18	Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Qiliang Shao,Zhenji Hu,Shaobo Chen,Pingxiuqi Chen,Jiafeng Xie	2017	3
19	Reliable Inversion in GF(2⁸) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Mehran Mozaffari Kermani,Amir Jalali,Reza Azarderakhsh,Jiafeng Xie,Kim‐Kwang Raymond Choo	2017	7
20	Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic IEEE Transactions on Computers ·Jiafeng Xie,Pramod Kumar Meher,Jianjun He	2012	24

About Jiafeng Xie

Jiafeng Xie is a scholar working on Artificial Intelligence, Information Systems and Hardware and Architecture, having authored 69 papers that have together received 683 indexed citations. Recurring topics across this work include Coding theory and cryptography (49 papers), Cryptography and Residue Arithmetic (39 papers), Cryptography and Data Security (35 papers), Cryptographic Implementations and Security (20 papers), Quantum Computing Algorithms and Architecture (7 papers), Physical Unclonable Functions (PUFs) and Hardware Security (4 papers), Low-power high-performance VLSI design (3 papers) and Numerical Methods and Algorithms (3 papers). The work is most often cited by research in Artificial Intelligence (476 citations), Information Systems (306 citations) and Hardware and Architecture (61 citations). Jiafeng Xie has collaborated with scholars based in United States, China and Taiwan. Frequent co-authors include Chiou‐Yng Lee, Pramod Kumar Meher, Anissa Sghaier, Medien Zeghid, Jeng‐Shyang Pan, Zhi‐Hong Mao, Ujjwal Guin, Mehran Mozaffari Kermani, Reza Azarderakhsh and Guanzheng Tan. Their work appears in journals such as IEEE Access, IEEE Transactions on Computers and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

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