Jean‐Luc Danger

4.4k total citations
130 papers, 1.3k citations indexed

About

Jean‐Luc Danger is a scholar working on Hardware and Architecture, Artificial Intelligence and Electrical and Electronic Engineering. According to data from OpenAlex, Jean‐Luc Danger has authored 130 papers receiving a total of 1.3k indexed citations (citations by other indexed papers that have themselves been cited), including 90 papers in Hardware and Architecture, 88 papers in Artificial Intelligence and 45 papers in Electrical and Electronic Engineering. Recurrent topics in Jean‐Luc Danger's work include Physical Unclonable Functions (PUFs) and Hardware Security (88 papers), Cryptographic Implementations and Security (77 papers) and Chaos-based Image/Signal Encryption (36 papers). Jean‐Luc Danger is often cited by papers focused on Physical Unclonable Functions (PUFs) and Hardware Security (88 papers), Cryptographic Implementations and Security (77 papers) and Chaos-based Image/Signal Encryption (36 papers). Jean‐Luc Danger collaborates with scholars based in France, United States and Japan. Jean‐Luc Danger's co-authors include Sylvain Guilley, Shivam Bhasin, Laurent Sauvage, Nidhal Selmane, Philippe Hoogvorst, Emmanuel Boutillon, Xuan Thuy Ngo, Naghmeh Karimi, Adel Ghazel and Maxime Nassar and has published in prestigious journals such as SHILAP Revista de lepidopterología, IEEE Transactions on Information Theory and IEEE Transactions on Communications.

In The Last Decade

Jean‐Luc Danger

122 papers receiving 1.3k citations

Peers

Jean‐Luc Danger

EEE

CVPR

Sylvain Guilley France

Lilian Bossuet France

Kaijie Wu United States

Kris Gaj United States

Tim Güneysu Germany

Naofumi Homma Japan

Yingjie Lao United States

Sanu Mathew United States

Himanshu Kaul United States

Giorgio Di Natale France

Sylvain Guilley France

Jean‐Luc Danger

1.1k ×1.3

1.3k ×1.7

514 ×0.9

EEE

486 ×1.5

CVPR

301 ×1.4

Citations per year, relative to Jean‐Luc Danger Jean‐Luc Danger (= 1×) peers Sylvain Guilley

Countries citing papers authored by Jean‐Luc Danger

Since Specialization

Citations

This map shows the geographic impact of Jean‐Luc Danger's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jean‐Luc Danger with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jean‐Luc Danger more than expected).

Fields of papers citing papers by Jean‐Luc Danger

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jean‐Luc Danger. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jean‐Luc Danger. The network helps show where Jean‐Luc Danger may publish in the future.

Co-authorship network of co-authors of Jean‐Luc Danger

This figure shows the co-authorship network connecting the top 25 collaborators of Jean‐Luc Danger. A scholar is included among the top collaborators of Jean‐Luc Danger based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jean‐Luc Danger. Jean‐Luc Danger is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Dutertre, Jean-Max, et al.. (2024). Software countermeasures against the multiple instructions skip fault model. Microelectronics Reliability. 155. 115370–115370.

Danger, Jean‐Luc, et al.. (2024). On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 32(5). 911–924. 2 indexed citations

Danger, Jean‐Luc, et al.. (2024). Multi-modal Pre-silicon Evaluation of Hardware Masking Styles. Journal of Electronic Testing. 40(6). 723–740.

Danger, Jean‐Luc, et al.. (2024). Attacking Multi-Tenant FPGAs Without Manual Placement and Routing. 367–372.

Danger, Jean‐Luc, et al.. (2023). Testing and reliability enhancement of security primitives: Methodology and experimental validation. Microelectronics Reliability. 147. 115055–115055. 1 indexed citations

Danger, Jean‐Luc, et al.. (2023). Aging-Induced Failure Prognosis via Digital Sensors. SPIRE - Sciences Po Institutional REpository. 703–708. 2 indexed citations

Danger, Jean‐Luc, et al.. (2023). A gem5 based Platform for Micro-Architectural Security Analysis. SPIRE - Sciences Po Institutional REpository. 91–99.

Danger, Jean‐Luc, et al.. (2023). Special Session: Security Verification & Testing for SR-Latch TRNGs. SPIRE - Sciences Po Institutional REpository. 1–10. 1 indexed citations

Mushtaq, Maria, et al.. (2023). WIP: AMICA: Attention-based Multi-Identifier model for asynchronous intrusion detection on Controller Area networks. 2 indexed citations

10.

Mushtaq, Maria, et al.. (2022). CAN-BERT do it? Controller Area Network Intrusion Detection System based on BERT Language Model. SPIRE - Sciences Po Institutional REpository. 1–8. 27 indexed citations

11.

Danger, Jean‐Luc, et al.. (2021). Reducing Aging Impacts in Digital Sensors via Run-Time Calibration. Journal of Electronic Testing. 37(5-6). 653–673. 4 indexed citations

12.

Danger, Jean‐Luc, et al.. (2021). Détection d'intrusion SOME/IP à l'aide de modèles séquentiels basés sur l'apprentissage profond dans les réseaux Ethernet automobiles. SPIRE - Sciences Po Institutional REpository. 20 indexed citations

13.

Rioul, Olivier, et al.. (2020). Challenge codes for physically unclonable functions with Gaussian delays: A maximum entropy problem. Advances in Mathematics of Communications. 14(3). 491–505. 1 indexed citations

14.

Carlet, Claude, et al.. (2019). Detecting Faults in Inner-Product Masking Scheme - IPM-FD: IPM with Fault Detection. SPIRE - Sciences Po Institutional REpository. 11. 17–0. 4 indexed citations

15.

Bhasin, Shivam, Jean‐Luc Danger, Tarik Graba, et al.. (2014). Physical security evaluation at an early design-phase: A side-channel aware simulation methodology. 13–20. 7 indexed citations

16.

Guilley, Sylvain, et al.. (2010). Far correlation-based EMA with a precharacterized leakage model. Design, Automation, and Test in Europe. 977–980. 11 indexed citations

17.

Nassar, Maxime, et al.. (2010). BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation. Design, Automation, and Test in Europe. 849–854. 38 indexed citations

18.

Guilley, Sylvain, Laurent Sauvage, Tarik Graba, et al.. (2008). Place-and-route impact on the security of DPL designs in FPGAs. SPIRE - Sciences Po Institutional REpository. 26–32. 16 indexed citations

19.

Krikidis, Ioannis, Jean‐Luc Danger, & Lírida Naviner. (2006). Reconfigurable Implementation Issues of a Detection Scheme for DS-CDMA High Data Rate Connections. 1. 695–699.

20.

Krikidis, Ioannis, Jean‐Luc Danger, & Lírida Naviner. (2005). A DS-CDMA multi-stage inter-path interference canceller for high bit rates. 405–408. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact