Jai-Ming Lin
- Electrical and Electronic Engineering top 10%
- Hardware and Architecture top 5%
- Computer Networks and Communications top 10%
- Industrial and Manufacturing Engineering top 10%
- Computer Graphics and Computer-Aided Design top 10%
- Topics
- VLSI and FPGA Design Techniques (10 papers)VLSI and Analog Circuit Testing (6 papers)Embedded Systems Design Techniques (5 papers)
- Cited by
- Hardware and ArchitectureElectrical and Electronic EngineeringComputer Graphics and Computer-Aided Design
- Journals
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsIEEE Transactions on Very Large Scale Integration (VLSI) SystemsACM Transactions on Design Automation of Electronic Systems
- Partner nations
- TaiwanUnited States
In The Last Decade
Jai-Ming Lin
9 papers receiving 359 citations
Peers
Comparison fields: 5 of 21
- Electrical and Electronic Engineering 342
- Hardware and Architecture 218
- Computer Networks and Communications 77
- Industrial and Manufacturing Engineering 41
- Computer Graphics and Computer-Aided Design 17
Countries citing papers authored by Jai-Ming Lin
This map shows the geographic impact of Jai-Ming Lin's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jai-Ming Lin with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jai-Ming Lin more than expected).
Fields of papers citing papers by Jai-Ming Lin
This network shows the impact of papers produced by Jai-Ming Lin. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jai-Ming Lin. The network helps show where Jai-Ming Lin may publish in the future.
Co-authorship network of co-authors of Jai-Ming Lin
This figure shows the co-authorship network connecting the top 25 collaborators of Jai-Ming Lin. A scholar is included among the top collaborators of Jai-Ming Lin based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jai-Ming Lin. Jai-Ming Lin is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 44 | |
| 2 | 33 | |
| 3 | 43 | |
| 4 | 1 | |
| 5 | 0 | |
| 6 | 1 | |
| 7 | 38 | |
| 8 | 185 | |
| 9 | 22 | |
| 10 | 5 |
About Jai-Ming Lin
Jai-Ming Lin is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications, having authored 10 papers that have together received 372 indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (10 papers), VLSI and Analog Circuit Testing (6 papers) and Embedded Systems Design Techniques (5 papers). The work is most often cited by research in Hardware and Architecture (218 citations), Electrical and Electronic Engineering (342 citations) and Computer Graphics and Computer-Aided Design (17 citations). Jai-Ming Lin has collaborated with scholars based in Taiwan and United States. Frequent co-authors include Yao‐Wen Chang, Guangming Wu, Jen‐Hui Chuang, Martin D. F. Wong and S. Prasad. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Design Automation of Electronic Systems.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.