J. Dielissen

2.3k citations

17 papers · 1.7k indexed · 1 hit paper · h-index 13

Computer Networks and Communications top 0.5%
Hardware and Architecture top 0.5%
Electrical and Electronic Engineering top 5%
Electronic, Optical and Magnetic Materials top 10%
Materials Chemistry

Co-authors: Kees Goossens A. Rădulescu E. Rijpkema P. Wielage J. van Meerbergen E. Waterlander A.P. Hekstra Bart Vermeulen
Topics: Interconnection Networks and Systems (9 papers)Embedded Systems Design Techniques (8 papers)Error Correcting Code Techniques (7 papers)
Cited by: Hardware and Architecture Computer Networks and Communications Electrical and Electronic Engineering
Journals: IEEE Communications Magazine IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on Circuits & Systems II Express Briefs
Partner nations: Netherlands Finland France

In The Last Decade

J. Dielissen

17 papers receiving 1.6k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

Æthereal Network on Chip:Concepts, Architectures, and Implementations

2005 654 citations Kees Goossens, J. Dielissen et al. IEEE Design & Test of Computers profile →

Peers

Countries citing papers authored by J. Dielissen

Since Specialization

Citations

This map shows the geographic impact of J. Dielissen's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Dielissen with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Dielissen more than expected).

Fields of papers citing papers by J. Dielissen

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Dielissen. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Dielissen. The network helps show where J. Dielissen may publish in the future.

Co-authorship network of co-authors of J. Dielissen

This figure shows the co-authorship network connecting the top 25 collaborators of J. Dielissen. A scholar is included among the top collaborators of J. Dielissen based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with J. Dielissen. J. Dielissen is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

17 of 17 papers shown

#	Work	Indexed citations
1	Multistandard FEC Decoders for Wireless Devices 2008 ·IEEE Transactions on Circuits & Systems II Express Briefs ·J. Dielissen,(unknown),(unknown),Kees van Berkel	14
2	Non-fractional parallelism in LDPC decoder implementations 2007 ·Design, Automation, and Test in Europe ·J. Dielissen,A.P. Hekstra	5
3	Non-fractional parallelism in LDPC Decoder implementations 2007 ·J. Dielissen,A.P. Hekstra	5
4	Low cost LDPC decoder for DVB-S2 2006 ·J. Dielissen,A.P. Hekstra,(unknown)	64
5	A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification 2005 ·Design, Automation, and Test in Europe ·Kgw Kees Goossens,J. Dielissen,(unknown),(unknown),(unknown),E. Rijpkema	129
6	Æthereal Network on Chip:Concepts, Architectures, and Implementationsbreakdown → 2005 ·IEEE Design & Test of Computers ·Kees Goossens,J. Dielissen,A. Rădulescu	654
7	An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration 2004 ·Design, Automation, and Test in Europe ·A. Rădulescu,J. Dielissen,Kees Goossens,E. Rijpkema,P. Wielage	53
8	A scalable architecture for LDPC decoding 2004 ·Design, Automation, and Test in Europe ·(unknown),J. Dielissen,M.J.M. Heijligers,A.P. Hekstra,Jos Huisken	32
9	A scalable architecture for LDPC decoding 2004 ·Proceedings Design, Automation and Test in Europe Conference and Exhibition ·(unknown),J. Dielissen,(unknown),A.P. Hekstra,Jos Huisken	28
10	An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration 2004 ·Proceedings Design, Automation and Test in Europe Conference and Exhibition ·A. Rădulescu,J. Dielissen,Kees Goossens,E. Rijpkema,(unknown)	35
11	An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration 2004 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·A. Rădulescu,J. Dielissen,(unknown),Om Prakash Gangwal,E. Rijpkema,P. Wielage,Kees Goossens	38
12	Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip 2003 ·Design, Automation, and Test in Europe ·E. Rijpkema,Kees Goossens,A. Rădulescu,J. Dielissen,J. van Meerbergen,P. Wielage,E. Waterlander	281
13	Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip 2003 ·2003 Design, Automation and Test in Europe Conference and Exhibition ·E. Rijpkema,Kees Goossens,A. Rădulescu,J. Dielissen,J. van Meerbergen,P. Wielage,E. Waterlander	148
14	Bringing communication networks on a chip: test and verification implications 2003 ·IEEE Communications Magazine ·Bart Vermeulen,J. Dielissen,Kees Goossens,C. Ciordas	106
15	Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip 2003 ·IEE Proceedings - Computers and Digital Techniques ·E. Rijpkema,Kees Goossens,(unknown),J. Dielissen,J. van Meerbergen,P. Wielage,E. Waterlander	87
16	Power-efficient application-specific VLIW processor for turbo decoding 2002 ·TU/e Research Portal ·(unknown),J. Dielissen,(unknown),(unknown),Jos Huisken,(unknown),J. van Meerbergen	11
17	Implementation issues of 3rd generation mobile communication turbo decoding 2000 ·Munich Personal RePEc Archive (Ludwig Maximilian University of Munich) ·J. Dielissen,Jos Huisken	3

About J. Dielissen

J. Dielissen is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering, having authored 17 papers that have together received 1.7k indexed citations. Recurring topics across this work include Interconnection Networks and Systems (9 papers), Embedded Systems Design Techniques (8 papers) and Error Correcting Code Techniques (7 papers). The work is most often cited by research in Hardware and Architecture (1.3k citations), Computer Networks and Communications (1.6k citations) and Electrical and Electronic Engineering (689 citations). J. Dielissen has collaborated with scholars based in Netherlands, Finland and France. Frequent co-authors include Kees Goossens, A. Rădulescu, E. Rijpkema, P. Wielage, J. van Meerbergen, E. Waterlander, A.P. Hekstra, Bart Vermeulen, C. Ciordas and Kgw Kees Goossens. Their work appears in journals such as IEEE Communications Magazine, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Circuits & Systems II Express Briefs.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact