G. Feygin

529 total citations
20 papers, 346 citations indexed

About

G. Feygin is a scholar working on Electrical and Electronic Engineering, Artificial Intelligence and Computer Networks and Communications. According to data from OpenAlex, G. Feygin has authored 20 papers receiving a total of 346 indexed citations (citations by other indexed papers that have themselves been cited), including 14 papers in Electrical and Electronic Engineering, 9 papers in Artificial Intelligence and 8 papers in Computer Networks and Communications. Recurrent topics in G. Feygin's work include Algorithms and Data Compression (8 papers), Advancements in PLL and VCO Technologies (8 papers) and Error Correcting Code Techniques (7 papers). G. Feygin is often cited by papers focused on Algorithms and Data Compression (8 papers), Advancements in PLL and VCO Technologies (8 papers) and Error Correcting Code Techniques (7 papers). G. Feygin collaborates with scholars based in United States, Canada and South Korea. G. Feygin's co-authors include P.G. Gulak, Paul Chow, Robert Bogdan Staszewski, J. Wallberg, Chih-Ming Hung, Mitch Entezari, Mostafa El‐Khamy, Inyup Kang, Hessam Mahdavifar and Dirk Leipold and has published in prestigious journals such as IEEE Transactions on Information Theory, IEEE Transactions on Signal Processing and IEEE Transactions on Communications.

In The Last Decade

G. Feygin

20 papers receiving 310 citations

Peers

Countries citing papers authored by G. Feygin

Since Specialization

Citations

This map shows the geographic impact of G. Feygin's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by G. Feygin with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites G. Feygin more than expected).

Fields of papers citing papers by G. Feygin

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by G. Feygin. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by G. Feygin. The network helps show where G. Feygin may publish in the future.

Co-authorship network of co-authors of G. Feygin

This figure shows the co-authorship network connecting the top 25 collaborators of G. Feygin. A scholar is included among the top collaborators of G. Feygin based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with G. Feygin. G. Feygin is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Automatic Restriction of Radiated Power in 5G Handsets based on Proximity Detection to Comply with Exposure Limits 2024 ·Oren Eliezer, G. Feygin, Viduneth Ariyarathna, (unknown), P. Dayal, (unknown), (unknown), (unknown), (unknown), (unknown)	1
2	A 14-nm Low-Cost IF Transceiver IC with Low-Jitter LO and Flexible Calibration Architecture for 5G FR2 Mobile Applications 2023 ·Wanghua Wu, (unknown), (unknown), Taeyoung Kang, (unknown), (unknown), (unknown), Ashutosh Verma, (unknown), Chih-Wei Yao, (unknown), G. Feygin, P. Dayal, Kee-Bong Song, (unknown)	1
3	Relaxed Polar Codes 2017 ·IEEE Transactions on Information Theory ·Mostafa El‐Khamy, Hessam Mahdavifar, G. Feygin, Jungwon Lee, Inyup Kang	25
4	Relaxed channel polarization for reduced complexity polar coding 2015 ·Mostafa El‐Khamy, Hessam Mahdavifar, G. Feygin, (unknown), Inyup Kang	9
5	Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter 2011 ·(unknown), Robert Bogdan Staszewski, G. Feygin, Oren Eliezer, M.F. Frechétte, Poras T. Balsara	2
6	A 65nm CMOS DCXO system for generating 38.4MHz and a real time clock from a single crystal in 0.09mm² 2010 ·Danielle Griffith, (unknown), G. Feygin, Ahmed N. Mohieldin, (unknown)	25
7	A 0.8mm<sup>2</sup> all-digital SAW-less polar transmitter in 65nm EDGE SoC 2010 ·(unknown), Robert Bogdan Staszewski, Oren Eliezer, S. Rezeq, Khurram Waheed, Mitch Entezari, G. Feygin, S. Vemulapalli, (unknown), Chih-Ming Hung, N. Barton, Imran Bashir, K. Maggio, M.F. Frechétte, Meng-Chang Lee, J. Wallberg, P. Cruise, (unknown)	17
8	A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS 2009 ·K. Muhammad, Chih-Ming Hung, Dirk Leipold, T. Mayhugh, I. Elahi, I. Deng, C. Fernando, (unknown), Thomas W Murphy, J. Wallberg, Robert Bogdan Staszewski, Shawn D. Larson, T. Jung, P. Cruise, (unknown), S. Vemulapalli, Oren Eliezer, G. Feygin, (unknown), K. Maggio	8
9	LMS-based calibration of an RF digitally controlled oscillator for mobile phones 2006 ·IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ·Robert Bogdan Staszewski, J. Wallberg, Chih-Ming Hung, G. Feygin, Mitch Entezari, Dirk Leipold	38
10	Implementation of a High Speed Digital Band-Pass Sigma-Delta Modulator for a Wireless Transmitter 2006 ·(unknown), G. Feygin, S. Rezeq, Robert Bogdan Staszewski, S. Vemulapalli, Oren Eliezer, Poras T. Balsara	6
11	Architectural advances in the VLSI implementation of arithmetic coding for binary image compression 2002 ·G. Feygin, P.G. Gulak, Paul Chow	11
12	A VLSI implementation of a cascade Viterbi decoder with traceback 2002 ·1993 IEEE International Symposium on Circuits and Systems ·G. Feygin, Paul Chow, P.G. Gulak, (unknown), (unknown), (unknown), (unknown), Satnam Singh, (unknown), Steven J. E. Wilton	2
13	A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation 2002 ·G. Feygin, K. Nagaraj, (unknown), (unknown), (unknown), David Martin, (unknown), Shanthi Pavan	6
14	Minimizing error and VLSI complexity in the multiplication free approximation of arithmetic coding 2002 ·G. Feygin, P.G. Gulak, Paul Chow	8
15	A 160-MHz analog equalizer for magnetic disk read channels 1997 ·IEEE Journal of Solid-State Circuits ·(unknown), (unknown), G. Feygin, Robert Bogdan Staszewski, R.L. Pierson, (unknown), M. de Wit, K. Nagaraj	37
16	Minimizing excess code length and VLSI complexity in the multiplication free approximation of arithmetic coding 1994 ·Information Processing & Management ·G. Feygin, P.G. Gulak, Paul Chow	8
17	A multiprocessor architecture for Viterbi decoders with linear speedup 1993 ·IEEE Transactions on Signal Processing ·G. Feygin, P.G. Gulak, Paul Chow	19
18	Architectural tradeoffs for survivor sequence memory management in Viterbi decoders 1993 ·IEEE Transactions on Communications ·G. Feygin, P.G. Gulak	93
19	Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up 1991 ·G. Feygin, P.G. Gulak, Paul Chow	7
20	Survivor sequence memory management in Viterbi decoders 1991 ·G. Feygin, P.G. Gulak	23

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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