Steven J. E. Wilton

5.6k total citations · 1 hit paper
168 papers, 3.4k citations indexed

About

Steven J. E. Wilton is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, Steven J. E. Wilton has authored 168 papers receiving a total of 3.4k indexed citations (citations by other indexed papers that have themselves been cited), including 143 papers in Hardware and Architecture, 136 papers in Electrical and Electronic Engineering and 31 papers in Computer Networks and Communications. Recurrent topics in Steven J. E. Wilton's work include VLSI and FPGA Design Techniques (110 papers), Embedded Systems Design Techniques (92 papers) and VLSI and Analog Circuit Testing (74 papers). Steven J. E. Wilton is often cited by papers focused on VLSI and FPGA Design Techniques (110 papers), Embedded Systems Design Techniques (92 papers) and VLSI and Analog Circuit Testing (74 papers). Steven J. E. Wilton collaborates with scholars based in Canada, United Kingdom and United States. Steven J. E. Wilton's co-authors include Norman P. Jouppi, Julien Lamoureux, Wayne Luk, Jeffrey Goeders, Eddie Hung, Philip H. W. Leong, Andy Yan, George A. Constantinides, R. Saleh and Guy Lemieux and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Computers.

In The Last Decade

Steven J. E. Wilton

156 papers receiving 3.2k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

CACTI: an enhanced cache access and cycle time model

1996 649 citations Steven J. E. Wilton et al. profile →

Peers

Steven J. E. Wilton

HA

EEE

CNC

AI

CTM

Zhonghai Lu Sweden

Ahmed Hemani Sweden

Georgi Gaydadjiev Netherlands

Pedro Reviriego Spain

Preeti Ranjan Panda India

Cristina Silvano Italy

Valeria Bertacco United States

Juan Antonio Maestro Spain

T. Austin United States

Ian Kuon Canada

Zhonghai Lu Sweden

Steven J. E. Wilton

1.6k ×0.6

HA

1.3k ×0.5

EEE

2.2k ×1.8

CNC

193 ×1.0

AI

147 ×1.0

CTM

Citations per year, relative to Steven J. E. Wilton Steven J. E. Wilton (= 1×) peers Zhonghai Lu

Countries citing papers authored by Steven J. E. Wilton

Since Specialization

Citations

This map shows the geographic impact of Steven J. E. Wilton's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Steven J. E. Wilton with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Steven J. E. Wilton more than expected).

Fields of papers citing papers by Steven J. E. Wilton

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Steven J. E. Wilton. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Steven J. E. Wilton. The network helps show where Steven J. E. Wilton may publish in the future.

Co-authorship network of co-authors of Steven J. E. Wilton

This figure shows the co-authorship network connecting the top 25 collaborators of Steven J. E. Wilton. A scholar is included among the top collaborators of Steven J. E. Wilton based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Steven J. E. Wilton. Steven J. E. Wilton is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

1.

Wilton, Steven J. E., et al.. (2024). Enabling Risk Management of Machine Learning Predictions for FPGA Routability. 1–9.

2.

Wilton, Steven J. E., et al.. (2024). Machine Learning VLSI CAD Experiments Should Consider Atomic Data Groups. 1–8.

3.

Wilton, Steven J. E., et al.. (2023). T-RecX. 123–133. 8 indexed citations

4.

Wilton, Steven J. E., et al.. (2023). Reformulating the FPGA Routability Prediction Problem with Machine Learning. 230–232. 1 indexed citations

5.

Wilton, Steven J. E., et al.. (2023). Online Training from Streaming Data with Concept Drift on FPGAs. 25. 1–8.

6.

Que, Zhiqiang, et al.. (2019). Towards In-Circuit Tuning of Deep Learning Designs. Spiral (Imperial College London). 1–6. 1 indexed citations

7.

Goeders, Jeffrey & Steven J. E. Wilton. (2015). Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. 127–134. 29 indexed citations

8.

Campbell, Chris, et al.. (2013). STUDENT PERSPECTIVES ON GRADUATE ATTRIBUTES. Proceedings of the Canadian Engineering Education Association (CEEA). 2 indexed citations

9.

Hung, Eddie, et al.. (2013). Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. 45–52. 32 indexed citations

10.

Gort, Marcel, Flavio M. De Paula, Tor M. Aamodt, et al.. (2011). Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20(11). 1997–2010. 3 indexed citations

11.

Wilton, Steven J. E., et al.. (2009). Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. ACM Transactions on Reconfigurable Technology and Systems. 1(4). 1–20. 3 indexed citations

12.

Lemieux, Guy, et al.. (2009). Congestion-driven regional re-clustering for low-cost FPGAs. 167–174. 1 indexed citations

13.

Yu, Chi Wai, et al.. (2009). Floating-Point FPGA: Architecture and Modeling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17(12). 1709–1718. 49 indexed citations

14.

Jamieson, Peter, Wayne Luk, Steven J. E. Wilton, & George A. Constantinides. (2009). An energy and power consumption analysis of FPGA routing architectures. 324–327. 36 indexed citations

15.

Smecher, G., Steven J. E. Wilton, & Guy Lemieux. (2009). Self-hosted placement for massively parallel processor arrays. 159–166. 2 indexed citations

16.

Yu, Chi Wai, Julien Lamoureux, Steven J. E. Wilton, Philip H. W. Leong, & Wayne Luk. (2008). The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. International Journal of Reconfigurable Computing. 2008. 1–10. 6 indexed citations

17.

Paula, Flavio M. De, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, & Jin Yang. (2008). BackSpace: Formal Analysis for Post-Silicon Debug. 1–10. 61 indexed citations

18.

Wilton, Steven J. E. & André DeHon. (2006). Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays. 3 indexed citations

19.

Lamoureux, Julien & Steven J. E. Wilton. (2006). Architecture and CAD for FPGA Clock Networks. 1. 1–2. 2 indexed citations

20.

Lamoureux, Julien & Steven J. E. Wilton. (2003). On the Interaction Between Power-Aware FPGA CAD Algorithms. International Conference on Computer Aided Design. 701–708. 75 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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