D. Lanneer

720 total citations
20 papers, 316 citations indexed

About

D. Lanneer is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering. According to data from OpenAlex, D. Lanneer has authored 20 papers receiving a total of 316 indexed citations (citations by other indexed papers that have themselves been cited), including 17 papers in Hardware and Architecture, 6 papers in Computer Networks and Communications and 5 papers in Electrical and Electronic Engineering. Recurrent topics in D. Lanneer's work include Embedded Systems Design Techniques (16 papers), Parallel Computing and Optimization Techniques (12 papers) and Interconnection Networks and Systems (6 papers). D. Lanneer is often cited by papers focused on Embedded Systems Design Techniques (16 papers), Parallel Computing and Optimization Techniques (12 papers) and Interconnection Networks and Systems (6 papers). D. Lanneer collaborates with scholars based in Belgium, Netherlands and Italy. D. Lanneer's co-authors include Gert Goossens, Johan Van Praet, H. De Man, Hugo De Man, Werner Geurts, Marco Cornero, Francky Catthoor, Pierre Paulin, J. van Meerbergen and R. Jonckheere and has published in prestigious journals such as Proceedings of the IEEE, Microelectronic Engineering and ACM Transactions on Design Automation of Electronic Systems.

In The Last Decade

D. Lanneer

19 papers receiving 289 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
D. Lanneer Belgium 12 259 101 97 31 25 20 316
Johan Van Praet Belgium 7 251 1.0× 117 1.2× 64 0.7× 23 0.7× 16 0.6× 8 290
Werner Geurts Belgium 9 227 0.9× 114 1.1× 90 0.9× 18 0.6× 13 0.5× 18 263
Kiran Bondalapati United States 6 151 0.6× 111 1.1× 73 0.8× 23 0.7× 30 1.2× 8 214
Peter Hochschild United States 8 224 0.9× 300 3.0× 121 1.2× 15 0.5× 48 1.9× 17 405
Derek Lockhart United States 8 249 1.0× 182 1.8× 119 1.2× 8 0.3× 23 0.9× 14 308
Peter Alfke United States 6 198 0.8× 50 0.5× 225 2.3× 26 0.8× 38 1.5× 17 304
Gaurav Mittal United States 8 174 0.7× 91 0.9× 120 1.2× 22 0.7× 50 2.0× 35 280
A. Gordon Smith United States 8 260 1.0× 201 2.0× 59 0.6× 12 0.4× 40 1.6× 27 311
Mingjun Wang United States 3 271 1.0× 215 2.1× 149 1.5× 19 0.6× 25 1.0× 5 390
Hiroki Honda Japan 11 159 0.6× 172 1.7× 36 0.4× 28 0.9× 28 1.1× 37 239

Countries citing papers authored by D. Lanneer

Since Specialization
Citations

This map shows the geographic impact of D. Lanneer's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Lanneer with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Lanneer more than expected).

Fields of papers citing papers by D. Lanneer

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Lanneer. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Lanneer. The network helps show where D. Lanneer may publish in the future.

Co-authorship network of co-authors of D. Lanneer

This figure shows the co-authorship network connecting the top 25 collaborators of D. Lanneer. A scholar is included among the top collaborators of D. Lanneer based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with D. Lanneer. D. Lanneer is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Goossens, Gert, D. Lanneer, Werner Geurts, & Johan Van Praet. (2006). Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite. 1–4. 14 indexed citations
2.
Catthoor, Francky, D. Lanneer, & H. De Man. (2003). Applications-specific microcoded architectures for efficient fixed-rate FFT. 1919–1922. 1 indexed citations
3.
Lanneer, D., et al.. (2003). Models for bit-true simulation and high-level synthesis of DSP applications. 5. 52–59. 1 indexed citations
4.
Claesen, Luc, Francky Catthoor, D. Lanneer, et al.. (2003). Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers. 14.7/1–14.7/4. 5 indexed citations
5.
Praet, Johan Van, D. Lanneer, Gert Goossens, Werner Geurts, & H. De Man. (2002). A graph based processor model for retargetable code generation. 102–107. 11 indexed citations
6.
Lanneer, D., et al.. (2002). Open-ended system for high-level synthesis of flexible signal processors. cad 6. 272–276. 11 indexed citations
7.
Lanneer, D., Marco Cornero, Gert Goossens, & H. De Man. (2002). An assignment technique for incompletely specified data-paths. 284–288.
8.
Praet, Johan Van, Gert Goossens, D. Lanneer, & H. De Man. (2002). Instruction set definition and instruction selection for ASIPs. 11–16. 38 indexed citations
9.
Lanneer, D., Marco Cornero, Gert Goossens, & H. De Man. (2002). Data routing: a paradigm for efficient data-path synthesis and code generation. 17–22. 16 indexed citations
10.
Praet, Johan Van, D. Lanneer, Werner Geurts, & Gert Goossens. (2001). Processor modeling and code selection for retargetable compilation. ACM Transactions on Design Automation of Electronic Systems. 6(3). 277–307. 11 indexed citations
11.
Goossens, Gert, et al.. (1997). Embedded software in real-time signal processing systems: design technologies. Proceedings of the IEEE. 85(3). 436–454. 46 indexed citations
12.
Praet, Johan Van, D. Lanneer, Werner Geurts, Gert Goossens, & Hugo De Man. (1996). Modelling hardware-specific data-types for simulation and compilation in HW/SW co-design. Epilepsia Open. 5(2). 255–262. 2 indexed citations
13.
Goossens, Gert, et al.. (1995). Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 9(1-2). 49–65. 13 indexed citations
14.
Lanneer, D., Marco Cornero, Gert Goossens, & H. De Man. (1994). Data routing: a paradigm for efficient data-path synthesis and code generation. 17–22. 37 indexed citations
15.
Praet, Johan Van, Gert Goossens, D. Lanneer, & Hugo De Man. (1994). Instruction set definition and instruction selection for ASIPs. 11–16. 70 indexed citations
16.
Lanneer, D., et al.. (1990). Open-ended system for high-level synthesis of flexible signal processors. European Design Automation Conference. 272–276. 17 indexed citations
17.
Meerbergen, J. van, Jos Huisken, P.E.R. Lippens, et al.. (1990). An integrated automatic design system for complex DSP algorithms. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 1(4). 265–278. 1 indexed citations
18.
Catthoor, Francky, D. Lanneer, & Hugo De Man. (1990). Efficient microcoded processor design for fixed rate DFT and FFT. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 1(4). 287–306. 2 indexed citations
19.
Catthoor, Francky, et al.. (1989). Type-handling in bit-true silicon compilation for DSP. 166–170. 4 indexed citations
20.
Jonckheere, R., et al.. (1986). Determination of the proximity parameters in electron beam lithography using doughnut-structures. Microelectronic Engineering. 5(1-4). 141–150. 16 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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