Christine Eisenbeis
About
In The Last Decade
Christine Eisenbeis
31 papers receiving 221 citations
Peers
Comparison fields: 5 of 27
- Hardware and Architecture 205
- Computer Networks and Communications 161
- Information Systems 46
- Artificial Intelligence 32
- Computational Theory and Mathematics 27
Countries citing papers authored by Christine Eisenbeis
This map shows the geographic impact of Christine Eisenbeis's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Christine Eisenbeis with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Christine Eisenbeis more than expected).
Fields of papers citing papers by Christine Eisenbeis
This network shows the impact of papers produced by Christine Eisenbeis. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Christine Eisenbeis. The network helps show where Christine Eisenbeis may publish in the future.
Co-authorship network of co-authors of Christine Eisenbeis
This figure shows the co-authorship network connecting the top 25 collaborators of Christine Eisenbeis. A scholar is included among the top collaborators of Christine Eisenbeis based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Christine Eisenbeis. Christine Eisenbeis is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 6 | |
| 2 | 15 | |
| 3 | 16 | |
| 4 | 3 | |
| 5 | 3 | |
| 6 | 4 | |
| 7 | Cyclic Register Pressure and Allocation for Modulo Scheduled Loops | 2 |
| 8 | 6 | |
| 9 | Flexible Issue Slot Assignment for VLIW Architectures | 12 |
| 10 | LoRA: a Package for Loop Optimal Register Allocation | 2 |
| 11 | Circular-arc Graph Coloring and Unrolling | 1 |
| 12 | GCDS: A Compiler Strategy for Trading Code Size Against Performance in Embedded Applications | 5 |
| 13 | 21 | |
| 14 | 24 | |
| 15 | 19 | |
| 16 | Using timed Petri net to analyze the maximum computation rate for loop programs | 1 |
| 17 | Decomposed software pipelining | 5 |
| 18 | A New timed Petri net model for loop scheduling with resource constraints | 1 |
| 19 | 11 | |
| 20 | Compile time optimization of memory and register usage on the Cray 2 | 2 |
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.