Tung-Chieh Chen

1.4k total citations
39 papers, 1.1k citations indexed

About

Tung-Chieh Chen is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Tung-Chieh Chen has authored 39 papers receiving a total of 1.1k indexed citations (citations by other indexed papers that have themselves been cited), including 37 papers in Electrical and Electronic Engineering, 25 papers in Hardware and Architecture and 2 papers in Computer Networks and Communications. Recurrent topics in Tung-Chieh Chen's work include VLSI and FPGA Design Techniques (37 papers), VLSI and Analog Circuit Testing (24 papers) and 3D IC and TSV technologies (17 papers). Tung-Chieh Chen is often cited by papers focused on VLSI and FPGA Design Techniques (37 papers), VLSI and Analog Circuit Testing (24 papers) and 3D IC and TSV technologies (17 papers). Tung-Chieh Chen collaborates with scholars based in Taiwan, Switzerland and United States. Tung-Chieh Chen's co-authors include Yao‐Wen Chang, Zhewei Jiang, Hsin-Chen Chen, Shyh-Chang Lin, Meng-Kai Hsu, Yifang Chen, Ping-Hung Yuh, Hsin-Ying Lee, Shengwei Yang and Mark Po-Hung Lin and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Journal of marine science and technology and NTUR (臺灣機構典藏).

In The Last Decade

Tung-Chieh Chen

36 papers receiving 1.0k citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Tung-Chieh Chen Taiwan	16	999	715	88	34	33	39	1.1k
Saurabh Adya United States	12	957 1.0×	725 1.0×	215 2.4×	41 1.2×	32 1.0×	25	1.1k
Wing-Kai Chow Hong Kong	14	484 0.5×	323 0.5×	67 0.8×	15 0.4×	46 1.4×	25	523
Yiu-Chung Wong United States	6	399 0.4×	280 0.4×	116 1.3×	20 0.6×	26 0.8×	11	457
Ismail Bustany United States	11	430 0.4×	306 0.4×	44 0.5×	24 0.7×	58 1.8×	24	468
Kun Yuan United States	12	525 0.5×	286 0.4×	73 0.8×	18 0.5×	27 0.8×	26	552
Eli Bozorgzadeh United States	17	534 0.5×	582 0.8×	364 4.1×	27 0.8×	8 0.2×	58	788
R. Nair United States	11	947 0.9×	577 0.8×	195 2.2×	42 1.2×	13 0.4×	18	1.1k
Shmuel Wimer Israel	12	474 0.5×	222 0.3×	162 1.8×	18 0.5×	70 2.1×	52	575
David W. Hightower United States	6	307 0.3×	204 0.3×	101 1.1×	31 0.9×	55 1.7×	11	383

Countries citing papers authored by Tung-Chieh Chen

Since Specialization

Citations

This map shows the geographic impact of Tung-Chieh Chen's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Tung-Chieh Chen with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Tung-Chieh Chen more than expected).

Fields of papers citing papers by Tung-Chieh Chen

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Tung-Chieh Chen. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Tung-Chieh Chen. The network helps show where Tung-Chieh Chen may publish in the future.

Co-authorship network of co-authors of Tung-Chieh Chen

This figure shows the co-authorship network connecting the top 25 collaborators of Tung-Chieh Chen. A scholar is included among the top collaborators of Tung-Chieh Chen based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Tung-Chieh Chen. Tung-Chieh Chen is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Chen, Yuyang, et al.. (2024). Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. 1–9.

Chen, Tung-Chieh. (2024). Introduction to the Panel on EDA Challenges at Advanced Technology Nodes. 61–61. 1 indexed citations

Chen, Tung-Chieh, et al.. (2020). Automatic Floorplanning for AI SoCs. 1–2. 8 indexed citations

Chang, Yao‐Wen, et al.. (2017). An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. International Conference on Computer Aided Design. 496–503. 3 indexed citations

Chang, Yao‐Wen, et al.. (2017). A novel damped-wave framework for macro placement. International Conference on Computer Aided Design. 504–511. 5 indexed citations

Lee, Hsin-Ying, et al.. (2017). NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37(3). 669–681. 51 indexed citations

Chang, Yao‐Wen, et al.. (2017). A novel damped-wave framework for macro placement. 504–511. 12 indexed citations

Chen, Hung-Ming, et al.. (2013). Efficient analog layout prototyping by layout reuse with routing preservation. International Conference on Computer Aided Design. 40–47. 5 indexed citations

Hsu, Meng-Kai, et al.. (2013). Routability-driven placement for hierarchical mixed-size circuit designs. 1–6. 29 indexed citations

10.

Chen, Tung-Chieh, et al.. (2013). Double patterning lithography-aware analog placement. 1–6. 6 indexed citations

11.

Chen, Tung-Chieh, et al.. (2008). An integrated nonlinear placement framework with congestion and porosity aware buffer planning. 702–707. 6 indexed citations

12.

Chen, Tung-Chieh, et al.. (2008). Effective Wire Models for X-Architecture Placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27(4). 654–658. 2 indexed citations

13.

Chen, Tung-Chieh, et al.. (2007). MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. Proceedings - ACM IEEE Design Automation Conference. 447–452. 1 indexed citations

14.

Chen, Tung-Chieh, et al.. (2006). A High-Quality Mixed-Size Analytical Placer Considering Preplaced Blocks and Density Constraints. Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design. 187–192. 15 indexed citations

15.

Chen, Tung-Chieh & Yao‐Wen Chang. (2006). Modern floorplanning based on B/sup */-tree and fast simulated annealing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25(4). 637–650. 119 indexed citations

16.

Chen, Tung-Chieh, Yao‐Wen Chang, & Shyh-Chang Lin. (2005). IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. International Conference on Computer Aided Design. 159–164. 38 indexed citations

17.

Chen, Tung-Chieh, Yao‐Wen Chang, & Shyh-Chang Lin. (2005). IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. 11. 159–164. 29 indexed citations

18.

Chen, Tung-Chieh, et al.. (2005). SoC test scheduling using the B*-tree based floorplanning technique. 2. 1188–1191.

19.

Chen, Tung-Chieh, Chiu‐Feng Lin, Chyuan-Yow Tseng, & Chung-Ying Chen. (2005). AN ADAPTIVE NONLINEAR FUEL INJECTION CONTROL ALGORITHM FOR MOTORCYCLE ENGINE. Journal of marine science and technology. 13(4). 1 indexed citations

20.

Chen, Tung-Chieh, et al.. (2005). SoC test scheduling using the B-tree based floorplanning technique. NTUR (臺灣機構典藏). 1188–1188. 10 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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