Minesh Patel

1.6k total citations
23 papers, 773 citations indexed

About

Minesh Patel is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, Minesh Patel has authored 23 papers receiving a total of 773 indexed citations (citations by other indexed papers that have themselves been cited), including 20 papers in Hardware and Architecture, 17 papers in Electrical and Electronic Engineering and 14 papers in Computer Networks and Communications. Recurrent topics in Minesh Patel's work include Parallel Computing and Optimization Techniques (15 papers), Advanced Memory and Neural Computing (8 papers) and Advanced Data Storage Technologies (8 papers). Minesh Patel is often cited by papers focused on Parallel Computing and Optimization Techniques (15 papers), Advanced Memory and Neural Computing (8 papers) and Advanced Data Storage Technologies (8 papers). Minesh Patel collaborates with scholars based in Switzerland, United States and Spain. Minesh Patel's co-authors include Onur Mutlu, Jeremie S. Kim, Hasan Hassan, Lois Orosa, Saugata Ghose, A. Giray Yağlıkçı, Haocong Luo, Hongzhong Zheng, Kevin Hsieh and Krishna T. Malladi and has published in prestigious journals such as IEEE Access, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Computer Architecture Letters.

In The Last Decade

Minesh Patel

22 papers receiving 682 citations

Peers

Minesh Patel
Omer Khan United States
Richard Fromm United States
Luis Lastras United States
Lois Orosa Switzerland
Lifan Xu United States
Hari Angepat United States
Allan Knies United States
Minesh Patel
Citations per year, relative to Minesh Patel Minesh Patel (= 1×) peers A. Giray Yağlıkçı

Countries citing papers authored by Minesh Patel

Since Specialization
Citations

This map shows the geographic impact of Minesh Patel's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Minesh Patel with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Minesh Patel more than expected).

Fields of papers citing papers by Minesh Patel

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Minesh Patel. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Minesh Patel. The network helps show where Minesh Patel may publish in the future.

Co-authorship network of co-authors of Minesh Patel

This figure shows the co-authorship network connecting the top 25 collaborators of Minesh Patel. A scholar is included among the top collaborators of Minesh Patel based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Minesh Patel. Minesh Patel is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Olgun, Ataberk, et al.. (2025). Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance. 849–866. 10 indexed citations
2.
Patel, Minesh, et al.. (2024). Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems. IEEE Access. 12. 196207–196239. 3 indexed citations
3.
Orosa, Lois, Ulrich Rührmair, A. Giray Yağlıkçı, et al.. (2024). SpyHammer: Understanding and Exploiting RowHammer Under Fine-Grained Temperature Variations. IEEE Access. 12. 80986–81003. 2 indexed citations
4.
Olgun, Ataberk, Hasan Hassan, A. Giray Yağlıkçı, et al.. (2023). DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42(12). 5098–5112. 26 indexed citations
5.
Yağlıkçı, A. Giray, Ataberk Olgun, Minesh Patel, et al.. (2022). HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips. 815–834. 32 indexed citations
6.
Wang, Yaohua, Lois Orosa, Yang Guo, et al.. (2020). FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching. 313–328. 42 indexed citations
7.
Luo, Haocong, Taha Shahroodi, Hasan Hassan, et al.. (2020). CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off. 666–679. 30 indexed citations
8.
Patel, Minesh, Jeremie S. Kim, Hasan Hassan, & Onur Mutlu. (2019). Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices. 13–25. 35 indexed citations
9.
Kim, Jeremie S., Minesh Patel, Hasan Hassan, Lois Orosa, & Onur Mutlu. (2019). D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput. 582–595. 52 indexed citations
10.
Orosa, Lois, Yaohua Wang, Mohammad Sadrosadati, et al.. (2019). Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices.. arXiv (Cornell University).
11.
Hassan, Hasan, Minesh Patel, Jeremie S. Kim, et al.. (2019). CROW. 129–142. 48 indexed citations
12.
Boroumand, Amirali, Saugata Ghose, Minesh Patel, et al.. (2019). CoNDA. 629–642. 49 indexed citations
13.
Kim, Jeremie S., Minesh Patel, Hasan Hassan, & Onur Mutlu. (2018). The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices. 194–207. 80 indexed citations
14.
Wang, Yaohua, Arash Tavakkol, Lois Orosa, et al.. (2018). Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration. 298–311. 32 indexed citations
15.
Patel, Minesh, Jeremie S. Kim, & Onur Cezmi Mutlu. (2017). The Reach Profiler (REAPER). ACM SIGARCH Computer Architecture News. 45(2). 255–268. 29 indexed citations
16.
Boroumand, Amirali, Saugata Ghose, Minesh Patel, et al.. (2016). LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory. IEEE Computer Architecture Letters. 16(1). 46–50. 99 indexed citations
17.
Patel, Minesh, et al.. (2007). High Performance Dependable Multiprocessor II. 1–22. 27 indexed citations
18.
Patel, Minesh, et al.. (2007). Technology Validation: NMP ST8 Dependable Multiprocessor Project II. 1–18. 15 indexed citations
19.
Ramos, Javier, et al.. (2006). Technology Validation: NMP ST8 Dependable Multiprocessor Project. 1–14. 9 indexed citations
20.
Ramos, Javier, Vikas A. Aggarwal, Minesh Patel, et al.. (2006). High-Performance, Dependable Multiprocessor. 1–13. 14 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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