Klaas Bult

3.6k citations

45 papers · 2.4k indexed · 1 hit paper · h-index 20

Impact in

Biomedical Engineering top 1%
- Analog and Mixed-Signal Circuit Design
Electrical and Electronic Engineering top 2%
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- CCD and CMOS Imaging Sensors
- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Semiconductor materials and devices

Papers in

Biomedical Engineering 38
- Analog and Mixed-Signal Circuit Design 38
Electrical and Electronic Engineering 42
- Advancements in Semiconductor Devices and Circuit Design 28
- CCD and CMOS Imaging Sensors 12
- Low-power high-performance VLSI design 10
- Semiconductor materials and devices 10
- Radio Frequency Integrated Circuit Design 8
- Advancements in PLL and VCO Technologies 7
- Semiconductor Lasers and Optical Devices 2

Co-authors: Govert Geelen Hans Wallinga Chi‐Hung Lin Aaron Buchwald J.A. Mulder Frank M. L. van der Goes Christopher M. Ward Kofi A. A. Makinwa
Journals: IEEE Journal of Solid-State Circuits (18 papers)IEEE Transactions on Circuits & Systems II Express Briefs (1 paper)Analog Integrated Circuits and Signal Processing (1 paper)Computer Standards & Interfaces (1 paper)European Solid-State Circuits Conference (1 paper)
Partner nations: Netherlands United States Israel

In The Last Decade

Klaas Bult

45 papers receiving 2.2k citations

Hit Papers

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A fast-settling CMOS op amp for SC circuits with 90-dB DC gain 1990 · 479 citations

Peers

Countries citing papers authored by Klaas Bult

Since Specialization

Citations

This map shows the geographic impact of Klaas Bult's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Klaas Bult with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Klaas Bult more than expected).

Fields of papers citing papers by Klaas Bult

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Klaas Bult. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Klaas Bult. The network helps show where Klaas Bult may publish in the future.

Co-authors

The 25 scholars most cited alongside Klaas Bult, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Klaas Bult Line = papers co-authored together Klaas Bult links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers IEEE Transactions on Circuits & Systems II Express Briefs ·Md Shakil Akter, Rohan Sehgal, Klaas Bult	2020	6
2	A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers IEEE Journal of Solid-State Circuits ·Rohan Sehgal, Frank van der Goes, Klaas Bult	2018	37
3	A capacitively-degenerated 100dB linear 20–150MS/s dynamic amplifier Md Shakil Akter, Kofi A. A. Makinwa, Klaas Bult	2017	14
4	A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction Md Shakil Akter, Rohan Sehgal, Frank van der Goes, Klaas Bult	2015	4
5	A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration Rohan Sehgal, Frank van der Goes, Klaas Bult	2014	4
6	A 1.5 mW 68 dB SNDR 80 Ms/s 2<formula formulatype="inline"> <tex Notation="TeX">$\times$</tex></formula> Interleaved Pipelined SAR ADC in 28 nm CMOS IEEE Journal of Solid-State Circuits ·Frank van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, J.A. Mulder, Sijia Wang, Klaas Bult	2014	69
7	A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3<formula formulatype="inline"> <tex Notation="TeX">$ {<} {-}$</tex></formula>58 dBc in 40 nm CMOS IEEE Journal of Solid-State Circuits ·Silvian Spiridon, J. van der Tang, Han Yan, Huafeng Chen, Davide Guermandi, Xiaodong Liu, E. Arslan, Frank van der Goes, Klaas Bult	2013	15
8	An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS IEEE Journal of Solid-State Circuits ·D. Vecchi, J.A. Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult	2011	44
9	A 12b 2.9GS/s DAC with IM3 ≪−60dBc beyond 1GHz in 65nm CMOS TU/e Research Portal ·Caiyan Lin, Frank van der Goes, J. Westra, J.A. Mulder, Yi‐Ting Lin, E. Arslan, Emre Ayranci, X. Liu, Klaas Bult	2009	40
10	Embedded analog-to-digital converters Klaas Bult	2009	12
11	Embedded Analog-to-Digital Converters Klaas Bult	2009	5
12	A 21mW 8b 125MS/s ADC occupying 0.09mm/sup 2/ in 0.13μm CMOS J.A. Mulder, Christopher M. Ward, Chi‐Hung Lin, D. Kruse, J. Westra, Marcel Lugthart, E. Arslan, R. van de Plassche, Klaas Bult, Frank M. L. van der Goes	2004	2
13	A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS IEEE Journal of Solid-State Circuits ·J.A. Mulder, Christopher M. Ward, Chi‐Hung Lin, D. Kruse, J. Westra, Marcel Lugthart, E. Arslan, R.J. van de Plassche, Klaas Bult, Frank M. L. van der Goes	2004	28
14	Embedded 240-MW 10-B 50-MS/S CMOS ADC in 1-MM∗∗2 Computer Standards & Interfaces ·Klaas Bult, Aaron Buchwald	1999	9
15	A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/ IEEE Journal of Solid-State Circuits ·Chi‐Hung Lin, Klaas Bult	1998	300
16	Analysis of a Current Mode MOST-only D-A Converter European Solid-State Circuits Conference ·P.E. de Haan, Sef van den Elshout, Eric A.M. Klumperink, Klaas Bult	1994	1
17	An inherently linear and compact MOST-only current division technique IEEE Journal of Solid-State Circuits ·Klaas Bult, Govert Geelen	1992	227
18	The CMOS gain-boosting technique Analog Integrated Circuits and Signal Processing ·Klaas Bult, Govert Geelen	1991	65
19	Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model IEEE Journal of Solid-State Circuits ·Hans Wallinga, Klaas Bult	1989	37
20	A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation IEEE Journal of Solid-State Circuits ·Klaas Bult, Hans Wallinga	1987	282

About Klaas Bult

Klaas Bult is a scholar working on Biomedical Engineering, Electrical and Electronic Engineering, Bioengineering, Hardware and Architecture and Computer Networks and Communications, having authored 45 papers that have together received 2.4k indexed citations. Recurring topics across this work include Analog and Mixed-Signal Circuit Design (38 papers), Advancements in Semiconductor Devices and Circuit Design (28 papers), CCD and CMOS Imaging Sensors (12 papers), Low-power high-performance VLSI design (10 papers), Semiconductor materials and devices (10 papers), Radio Frequency Integrated Circuit Design (8 papers), Advancements in PLL and VCO Technologies (7 papers) and Semiconductor Lasers and Optical Devices (2 papers). The work is most often cited by research in Biomedical Engineering (2.1k citations), Electrical and Electronic Engineering (2.3k citations), Hardware and Architecture (83 citations), Cellular and Molecular Neuroscience (135 citations) and Computer Networks and Communications (165 citations). Klaas Bult has collaborated with scholars based in Netherlands, United States and Israel. Frequent co-authors include Govert Geelen, Hans Wallinga, Chi‐Hung Lin, Aaron Buchwald, J.A. Mulder, Frank M. L. van der Goes, Christopher M. Ward, Kofi A. A. Makinwa, Chi‐Hung Lin and Xiaodong Liu. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits & Systems II Express Briefs, Analog Integrated Circuits and Signal Processing, Computer Standards & Interfaces and European Solid-State Circuits Conference.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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