K. Imamiya

483 total citations
25 papers, 259 citations indexed

About

K. Imamiya is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Computational Theory and Mathematics. According to data from OpenAlex, K. Imamiya has authored 25 papers receiving a total of 259 indexed citations (citations by other indexed papers that have themselves been cited), including 20 papers in Electrical and Electronic Engineering, 16 papers in Computer Networks and Communications and 6 papers in Computational Theory and Mathematics. Recurrent topics in K. Imamiya's work include Semiconductor materials and devices (19 papers), Advanced Data Storage Technologies (16 papers) and Advancements in Semiconductor Devices and Circuit Design (6 papers). K. Imamiya is often cited by papers focused on Semiconductor materials and devices (19 papers), Advanced Data Storage Technologies (16 papers) and Advancements in Semiconductor Devices and Circuit Design (6 papers). K. Imamiya collaborates with scholars based in Japan, United States and South Korea. K. Imamiya's co-authors include Ken Takeuchi, Koji Sakui, S. Satoh, S. Tanaka, S. Atsumi, M. Kuriyama, Shigeru Yamada, Akira Umezawa, H. Banba and Kiyomi Naruke and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electronics Packaging Manufacturing and 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

In The Last Decade

K. Imamiya

21 papers receiving 246 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
K. Imamiya Japan 9 225 88 86 60 29 25 259
Sudhanshu Khanna United States 9 346 1.5× 36 0.4× 54 0.6× 52 0.9× 99 3.4× 21 376
Joo-Sun Choi South Korea 9 278 1.2× 29 0.3× 19 0.2× 35 0.6× 38 1.3× 13 301
Tsutomu Yoshihara Japan 9 252 1.1× 14 0.2× 41 0.5× 46 0.8× 51 1.8× 54 285
D. Mizoguchi Japan 8 421 1.9× 91 1.0× 18 0.2× 56 0.9× 44 1.5× 13 442
Pradip Mandal India 11 380 1.7× 17 0.2× 26 0.3× 147 2.5× 50 1.7× 68 412
Sudhir S. Kudva United States 9 296 1.3× 24 0.3× 26 0.3× 101 1.7× 43 1.5× 23 317
Robert Sankman United States 5 301 1.3× 42 0.5× 21 0.2× 54 0.9× 79 2.7× 8 336
Seong-Jin Jang South Korea 9 272 1.2× 45 0.5× 15 0.2× 104 1.7× 53 1.8× 31 315
Noah Sturcken United States 10 374 1.7× 25 0.3× 39 0.5× 64 1.1× 33 1.1× 20 427

Countries citing papers authored by K. Imamiya

Since Specialization
Citations

This map shows the geographic impact of K. Imamiya's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Imamiya with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Imamiya more than expected).

Fields of papers citing papers by K. Imamiya

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K. Imamiya. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Imamiya. The network helps show where K. Imamiya may publish in the future.

Co-authorship network of co-authors of K. Imamiya

This figure shows the co-authorship network connecting the top 25 collaborators of K. Imamiya. A scholar is included among the top collaborators of K. Imamiya based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Imamiya. K. Imamiya is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Nakamura, Hiroshi, K. Imamiya, Tamio Ikehashi, et al.. (2005). A 125mm/sup 2/ 1Gb NAND flash memory with 10MB/s program throughput. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 2. 82–411. 2 indexed citations
2.
Nakamura, Hiroki, K. Imamiya, Tamio Ikehashi, et al.. (2003). A 125 mm/sup 2/ 1Gb NAND flash memory with 10 MB/s program throughput. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 1. 106–450. 2 indexed citations
3.
Kuriyama, M., S. Atsumi, Akira Umezawa, et al.. (2003). A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure. 152–153,. 3 indexed citations
4.
Ikehashi, Tamio, K. Imamiya, & Koji Sakui. (2003). Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND memory. 32. 225–234. 1 indexed citations
5.
Takeuchi, Ken, S. Satoh, K. Imamiya, et al.. (2003). A source-line programming scheme for low voltage operation NAND flash memories. 37–38. 2 indexed citations
6.
Imamiya, K., Hiroshi Nakamura, Ken Takeuchi, et al.. (2003). A 130 mm/sup 2/ 256 Mb NAND flash with shallow trench isolation technology. 112–113.
7.
8.
Imamiya, K., Hiroshi Nakamura, Tamio Ikehashi, et al.. (2002). A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed. IEEE Journal of Solid-State Circuits. 37(11). 1493–1501. 15 indexed citations
9.
Imamiya, K., Yoichi Iwata, Hiroshi Nakamura, et al.. (2002). A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM. 130–131,. 7 indexed citations
10.
Ikehashi, Tamio, et al.. (2002). A 60 ns access 32 kByte 3-transistor flash for low power embedded applications. 162–165. 1 indexed citations
11.
Takeuchi, Ken, S. Satoh, Tomoharu Tanaka, K. Imamiya, & Koji Sakui. (2002). A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories. 234–235. 10 indexed citations
12.
Sakui, Koji, K. Kanda, Hiroshi Nakamura, K. Imamiya, & J. Miyamoto. (2002). A sophisticated bit-by-bit verifying scheme for NAND EEPROMs. 236–237. 1 indexed citations
13.
Nakamura, Hiroshi, J. Miyamoto, K. Imamiya, & Yoichi Iwata. (2002). A novel sense amplifier for flexible voltage operation NAND flash memories. 71–72. 6 indexed citations
14.
Takeuchi, Ken, S. Satoh, K. Imamiya, & Koji Sakui. (2000). A source-line programming scheme for low-voltage operation NAND flash memories. IEEE Journal of Solid-State Circuits. 35(5). 672–681. 20 indexed citations
15.
Imamiya, K., Hiroshi Nakamura, Ken Takeuchi, et al.. (1999). A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology. IEEE Journal of Solid-State Circuits. 34(11). 1536–1543. 18 indexed citations
16.
Iwata, Yoichi, K. Imamiya, Hiroshi Nakamura, et al.. (1995). A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. IEEE Journal of Solid-State Circuits. 30(11). 1157–1164. 10 indexed citations
17.
Kuriyama, M., S. Atsumi, K. Imamiya, et al.. (1990). A 16-ns 1-Mb CMOS EPROM. IEEE Journal of Solid-State Circuits. 25(5). 1141–1146. 4 indexed citations
18.
Imamiya, K., J. Miyamoto, S. Atsumi, et al.. (1990). A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. IEEE Journal of Solid-State Circuits. 25(1). 72–78. 4 indexed citations
19.
Atsumi, S., M. Kuriyama, K. Imamiya, et al.. (1990). A 16 ns 1 Mb CMOS EPROM. 58–59.
20.
Tanaka, S., J. Miyamoto, S. Saito, et al.. (1987). A 4-Mbit CMOS EPROM. IEEE Journal of Solid-State Circuits. 22(5). 669–675. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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