J.–Y. Jou

566 total citations
18 papers, 366 citations indexed

About

J.–Y. Jou is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, J.–Y. Jou has authored 18 papers receiving a total of 366 indexed citations (citations by other indexed papers that have themselves been cited), including 15 papers in Electrical and Electronic Engineering, 14 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in J.–Y. Jou's work include VLSI and Analog Circuit Testing (12 papers), Low-power high-performance VLSI design (7 papers) and VLSI and FPGA Design Techniques (7 papers). J.–Y. Jou is often cited by papers focused on VLSI and Analog Circuit Testing (12 papers), Low-power high-performance VLSI design (7 papers) and VLSI and FPGA Design Techniques (7 papers). J.–Y. Jou collaborates with scholars based in United States, Taiwan and Germany. J.–Y. Jou's co-authors include Jacob A. Abraham, Kwang‐Ting Cheng, Kien A. Hua, Yao‐Wen Chang, Shailesh Sutarwala, Rolf Ernst, Chih‐Yang Hsu, J. D. Huang, Iris Hui-Ru Jiang and Sy‐Yen Kuo and has published in prestigious journals such as IEEE Transactions on Computers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

In The Last Decade

J.–Y. Jou

16 papers receiving 349 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
J.–Y. Jou United States	7	276	273	118	35	32	18	366
Dwight D. Hill United States	10	190 0.7×	203 0.7×	60 0.5×	12 0.3×	25 0.8×	32	284
A. Kalavade United States	6	103 0.4×	369 1.4×	207 1.8×	11 0.3×	35 1.1×	9	409
Tim Kogel Germany	10	113 0.4×	315 1.2×	229 1.9×	18 0.5×	24 0.8×	23	399
Seh-Woong Jeong South Korea	12	214 0.8×	280 1.0×	104 0.9×	51 1.5×	139 4.3×	28	394
Dimitris Nikolos Greece	10	285 1.0×	273 1.0×	41 0.3×	14 0.4×	26 0.8×	28	350
H.T. Vierhaus Germany	13	524 1.9×	512 1.9×	64 0.5×	48 1.4×	26 0.8×	109	595
Augustus K. Uht United States	10	140 0.5×	307 1.1×	194 1.6×	30 0.9×	15 0.5×	41	361
H.-K.T. Ma United States	9	401 1.5×	458 1.7×	57 0.5×	60 1.7×	101 3.2×	20	513
Phu Hoang United States	4	142 0.5×	320 1.2×	138 1.2×	9 0.3×	47 1.5×	6	358
Peter Bellows United States	4	86 0.3×	214 0.8×	89 0.8×	11 0.3×	38 1.2×	8	250

Countries citing papers authored by J.–Y. Jou

Since Specialization

Citations

This map shows the geographic impact of J.–Y. Jou's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J.–Y. Jou with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J.–Y. Jou more than expected).

Fields of papers citing papers by J.–Y. Jou

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J.–Y. Jou. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J.–Y. Jou. The network helps show where J.–Y. Jou may publish in the future.

Co-authorship network of co-authors of J.–Y. Jou

This figure shows the co-authorship network connecting the top 25 collaborators of J.–Y. Jou. A scholar is included among the top collaborators of J.–Y. Jou based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with J.–Y. Jou. J.–Y. Jou is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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18 of 18 papers shown

Chang, Yao‐Wen, et al.. (2006). RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25(10). 2258–2264. 27 indexed citations

Hsu, Chih‐Yang, et al.. (2003). An Efficient Power Model for IP-Level Complex Designs. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. 86(8). 2073–2080.

Wey, C.-L., et al.. (2003). OPAM: an efficient output phase assignment for multilevel logic minimization. 270–273. 1 indexed citations

Jou, J.–Y.. (2003). A testable PLA design with low overhead and ease of test generation. 450–453.

Ernst, Rolf, Shailesh Sutarwala, & J.–Y. Jou. (2003). TSG-a test system generator for debugging and regression test of high-level behavioral synthesis tools. 937–937. 1 indexed citations

Cheng, Kwang‐Ting & J.–Y. Jou. (2002). Functional test generation for finite state machines. Rare & Special e-Zone (The Hong Kong University of Science and Technology). 162–168. 29 indexed citations

Cheng, Kwang‐Ting & J.–Y. Jou. (2002). A single-state-transition fault model for sequential machines. Rare & Special e-Zone (The Hong Kong University of Science and Technology). c 20. 226–229. 23 indexed citations

Jou, J.–Y. & Kwang‐Ting Cheng. (2002). Timing-driven partial scan. Rare & Special e-Zone (The Hong Kong University of Science and Technology). 404–407. 20 indexed citations

Jiang, Iris Hui-Ru, et al.. (2001). Optimal reliable crosstalk driven interconnect optimization. International Conference on Computer Aided Design. 128–133. 1 indexed citations

10.

Jou, J.–Y., et al.. (2001). Efficient coverage analysis metric for HDL design validation. IEE Proceedings - Computers and Digital Techniques. 148(1). 1–6. 4 indexed citations

11.

Huang, J. D., J.–Y. Jou, & Wenwen Shen. (1999). Encoding in Roth-Karp decomposition with application to two-output LUT architecture. IEE Proceedings - Computers and Digital Techniques. 146(3). 131–131. 1 indexed citations

12.

Jou, J.–Y., et al.. (1998). Sensitisable-path-oriented clustered voltage scaling technique for low power. IEE Proceedings - Computers and Digital Techniques. 145(4). 301–301. 5 indexed citations

13.

Jou, J.–Y., et al.. (1996). BIST testability enhancement of system-level circuits: Experience with an industrial design. 219–224. 1 indexed citations

14.

Cheng, Kwang‐Ting & J.–Y. Jou. (1992). A functional fault model for sequential machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 11(9). 1065–1073. 38 indexed citations

15.

Ernst, Rolf, et al.. (1990). Simulation based verification of register-transfer level behavioral synthesis tools. European Design Automation Conference. 396–400. 1 indexed citations

16.

Jou, J.–Y. & Jacob A. Abraham. (1988). Fault-tolerant algorithms and architectures for real time signal processing. Proceedings of the International Conference on Parallel Processing. 1. 359–362. 4 indexed citations

17.

Jou, J.–Y. & Jacob A. Abraham. (1988). Fault-tolerant FFT networks. IEEE Transactions on Computers. 37(5). 548–561. 174 indexed citations

18.

Hua, Kien A., J.–Y. Jou, & Jacob A. Abraham. (1984). BUILT-IN TEST FOR VLSI FINITE-STATE MACHINES.. 292–297. 36 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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