Jai-Ming Lin

827 total citations
55 papers, 614 citations indexed

About

Jai-Ming Lin is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Jai-Ming Lin has authored 55 papers receiving a total of 614 indexed citations (citations by other indexed papers that have themselves been cited), including 53 papers in Electrical and Electronic Engineering, 32 papers in Hardware and Architecture and 3 papers in Computer Networks and Communications. Recurrent topics in Jai-Ming Lin's work include VLSI and FPGA Design Techniques (49 papers), VLSI and Analog Circuit Testing (26 papers) and Low-power high-performance VLSI design (22 papers). Jai-Ming Lin is often cited by papers focused on VLSI and FPGA Design Techniques (49 papers), VLSI and Analog Circuit Testing (26 papers) and Low-power high-performance VLSI design (22 papers). Jai-Ming Lin collaborates with scholars based in Taiwan, United States and Belgium. Jai-Ming Lin's co-authors include Soon-Jyh Chang, Yao‐Wen Chang, Jiajia Ma, Klaus Harms, Michael Marsch, Xixian Xie, Lifang Zhao, Eric Meggers, Jung‐Der Wang and Ying-Zu Lin and has published in prestigious journals such as Angewandte Chemie International Edition, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Jai-Ming Lin

52 papers receiving 597 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Jai-Ming Lin Taiwan	15	443	216	94	78	57	55	614
Pedro Gil Spain	14	431 1.0×	350 1.6×	64 0.7×	11 0.1×	106 1.9×	57	610
Jung Hwan Choi United States	13	288 0.7×	105 0.5×	13 0.1×	45 0.6×	33 0.6×	29	431
Jeonghun Cho South Korea	10	139 0.3×	73 0.3×	24 0.3×	23 0.3×	101 1.8×	71	333
Zhiyu Liu China	12	271 0.6×	47 0.2×	156 1.7×	19 0.2×	5 0.1×	28	491
Roy M. Jenevein United States	12	71 0.2×	97 0.4×	95 1.0×	32 0.4×	219 3.8×	33	395
Albert Ou United States	6	108 0.2×	139 0.6×	22 0.2×	8 0.1×	79 1.4×	10	300
Saurabh Joshi India	12	26 0.1×	51 0.2×	20 0.2×	24 0.3×	110 1.9×	32	436
Ehsan K. Ardestani United States	11	227 0.5×	211 1.0×	13 0.1×	14 0.2×	150 2.6×	29	391
Venkata Krishnan United States	13	166 0.4×	632 2.9×	24 0.3×	17 0.2×	591 10.4×	31	820

Countries citing papers authored by Jai-Ming Lin

Since Specialization

Citations

This map shows the geographic impact of Jai-Ming Lin's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jai-Ming Lin with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jai-Ming Lin more than expected).

Fields of papers citing papers by Jai-Ming Lin

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jai-Ming Lin. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jai-Ming Lin. The network helps show where Jai-Ming Lin may publish in the future.

Co-authorship network of co-authors of Jai-Ming Lin

This figure shows the co-authorship network connecting the top 25 collaborators of Jai-Ming Lin. A scholar is included among the top collaborators of Jai-Ming Lin based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jai-Ming Lin. Jai-Ming Lin is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Lin, Jai-Ming, et al.. (2024). Timing-Driven Analytical Placement According to Expected Cell Distribution Range. 177–184. 4 indexed citations

Kükner, Halil, Gioele Mirabelli, Sheng Yang, et al.. (2024). Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node. 1–4. 5 indexed citations

Lin, Jai-Ming, et al.. (2023). Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 31(9). 1308–1319.

Lin, Jai-Ming, et al.. (2023). HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique. 1–8. 2 indexed citations

Lin, Jai-Ming, et al.. (2022). A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS. 1–7.

Lin, Jai-Ming, et al.. (2022). Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs. 1–8. 1 indexed citations

Lin, Jai-Ming, et al.. (2021). Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs. 1–8. 15 indexed citations

Lin, Jai-Ming, et al.. (2019). A Novel Macro Placement Approach based on Simulated Evolution Algorithm. 1–7. 8 indexed citations

Lin, Jai-Ming, et al.. (2018). A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. 1–8. 16 indexed citations

10.

Lin, Jai-Ming, et al.. (2018). Macro-aware row-style power delivery network design for better routability. 1–8. 7 indexed citations

11.

Lin, Jai-Ming, et al.. (2018). Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. 1339–1344. 2 indexed citations

12.

Lin, Jai-Ming, et al.. (2018). Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27(1). 57–68. 8 indexed citations

13.

Chen, Zhaohong, Kuen-Jong Lee, Lih‐Yih Chiou, et al.. (2016). A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. 17–18. 2 indexed citations

14.

Lin, Jai-Ming, et al.. (2015). Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint. 29. 1–4. 1 indexed citations

15.

Lin, Jai-Ming, et al.. (2011). Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction. Asia and South Pacific Design Automation Conference. 527–532. 3 indexed citations

16.

Lin, Jai-Ming, et al.. (2010). Performance-driven analog placement considering boundary constraint. 292–297. 23 indexed citations

17.

Lin, Jai-Ming, Hsin‐Lung Chen, & Yao‐Wen Chang. (2003). Arbitrary convex and concave rectilinear module packing using TCG. 220. 69–75. 4 indexed citations

18.

Lin, Jai-Ming & Yao‐Wen Chang. (2002). TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. 842–847. 9 indexed citations

19.

Lin, Jai-Ming, Hsin‐Lung Chen, & Yao‐Wen Chang. (2002). Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10(6). 886–901. 10 indexed citations

20.

Chang, Yao‐Wen, Jai-Ming Lin, & Martin D. F. Wong. (2001). Matching-based algorithm for FPGA channel segmentation design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20(6). 784–791. 7 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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