Jaeyong Chung

671 total citations
61 papers, 474 citations indexed

About

Jaeyong Chung is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Vision and Pattern Recognition. According to data from OpenAlex, Jaeyong Chung has authored 61 papers receiving a total of 474 indexed citations (citations by other indexed papers that have themselves been cited), including 39 papers in Electrical and Electronic Engineering, 32 papers in Hardware and Architecture and 10 papers in Computer Vision and Pattern Recognition. Recurrent topics in Jaeyong Chung's work include VLSI and Analog Circuit Testing (21 papers), Low-power high-performance VLSI design (12 papers) and Advanced Memory and Neural Computing (11 papers). Jaeyong Chung is often cited by papers focused on VLSI and Analog Circuit Testing (21 papers), Low-power high-performance VLSI design (12 papers) and Advanced Memory and Neural Computing (11 papers). Jaeyong Chung collaborates with scholars based in South Korea, United States and Spain. Jaeyong Chung's co-authors include Jacob A. Abraham, Ryuichiro Yoshie, Taichi Shirasawa, Henry Gardner, Woochul Kang, Joon-Sung Yang, Jinjun Xiong, Vladimir Zolotov, Phuoc Pham and Joon-Sung Park and has published in prestigious journals such as IEEE Access, IEEE Transactions on Computers and Hearing Research.

In The Last Decade

Jaeyong Chung

57 papers receiving 453 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Jaeyong Chung South Korea 11 214 168 118 82 66 61 474
Xing Fu China 13 88 0.4× 153 0.9× 29 0.2× 21 0.3× 14 0.2× 42 494
Duan Zhao China 12 191 0.9× 20 0.1× 23 0.2× 26 0.3× 16 0.2× 35 443
Shahzad Muzaffar United Arab Emirates 9 250 1.2× 38 0.2× 34 0.3× 58 0.7× 5 0.1× 40 430
Shuang Gao China 11 90 0.4× 11 0.1× 12 0.1× 31 0.4× 72 1.1× 41 326
Tianyu Jia China 12 235 1.1× 101 0.6× 11 0.1× 75 0.9× 31 0.5× 76 494
Mirco Ravanelli Canada 7 81 0.4× 10 0.1× 17 0.1× 85 1.0× 11 0.2× 16 683
Min Shi China 10 32 0.1× 11 0.1× 23 0.2× 208 2.5× 21 0.3× 53 338

Countries citing papers authored by Jaeyong Chung

Since Specialization
Citations

This map shows the geographic impact of Jaeyong Chung's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jaeyong Chung with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jaeyong Chung more than expected).

Fields of papers citing papers by Jaeyong Chung

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jaeyong Chung. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jaeyong Chung. The network helps show where Jaeyong Chung may publish in the future.

Co-authorship network of co-authors of Jaeyong Chung

This figure shows the co-authorship network connecting the top 25 collaborators of Jaeyong Chung. A scholar is included among the top collaborators of Jaeyong Chung based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jaeyong Chung. Jaeyong Chung is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Kong, Yoon, et al.. (2025). Reducing Errors and Powers in LPDDR for DNN Inference: A Compression and IECC-Based Approach. Journal of Systems Architecture. 163. 103409–103409.
2.
Chung, Jaeyong, et al.. (2024). FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach. Journal of Systems Architecture. 155. 103260–103260.
3.
Chung, Jaeyong, et al.. (2024). Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 32(7). 1205–1215. 4 indexed citations
4.
Pham, Phuoc, Jacob A. Abraham, & Jaeyong Chung. (2021). Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer. IEEE Access. 9. 47194–47203. 14 indexed citations
5.
Abraham, Jacob A., et al.. (2020). A Neural Network Decomposition Algorithm for Mapping on Crossbar-Based Computing Systems. Electronics. 9(9). 1526–1526.
6.
Kang, Yong-Shin, et al.. (2020). InSight: An FPGA-Based Neuromorphic Computing System for Deep Neural Networks. Journal of Low Power Electronics and Applications. 10(4). 36–36. 4 indexed citations
7.
Kang, Woochul & Jaeyong Chung. (2018). Power- and Time-Aware Deep Learning Inference for Mobile Embedded Devices. IEEE Access. 7. 3778–3789. 5 indexed citations
8.
Yang, Sunggu, Jaeyong Chung, Sung Hun Jin, Shaowen Bao, & Sungchil Yang. (2018). A circuit mechanism of time-to-space conversion for perception. Hearing Research. 366. 32–37. 5 indexed citations
9.
Chung, Jaeyong, et al.. (2016). Simplifying deep neural networks for neuromorphic architectures. 1–6. 22 indexed citations
10.
Kang, Woochul & Jaeyong Chung. (2016). Energy-efficient response time management for embedded databases. Real-Time Systems. 53(2). 228–253. 7 indexed citations
11.
Kang, Woochul & Jaeyong Chung. (2015). QoS Management for Embedded Databases in Multicore-Based Embedded Systems. Mobile Information Systems. 2015. 1–14. 4 indexed citations
12.
Chung, Jaeyong & Jibum Kim. (2015). Segment Delay Learning From Quantized Path Delay Measurements. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34(6). 1038–1042. 3 indexed citations
13.
Chung, Jaeyong, Joon-Sung Park, & Jacob A. Abraham. (2012). A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21(2). 281–291. 6 indexed citations
14.
Chung, Jaeyong & Jacob A. Abraham. (2012). Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31(4). 485–496. 4 indexed citations
15.
Chung, Jaeyong, Jinjun Xiong, Vladimir Zolotov, & Jacob A. Abraham. (2011). Path criticality computation in parameterized statistical timing analysis. Asia and South Pacific Design Automation Conference. 249–254. 5 indexed citations
16.
Chung, Jaeyong, et al.. (2010). A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. 17. 145–150. 4 indexed citations
17.
Chung, Jaeyong & Jacob A. Abraham. (2009). A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. 321–327. 3 indexed citations
18.
Chung, Jaeyong & Jacob A. Abraham. (2009). Recursive Path Selection for Delay Fault Testing. 65–70. 7 indexed citations
19.
20.
Chung, Jaeyong. (2006). Numerical Simulation of Flow Past a Low-Rise Building Using the Modified DES model – The TL/LES Model. 218–228.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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