Fule Li

1.3k citations

111 papers · 519 indexed · h-index 12

Impact in

Electrical and Electronic Engineering top 10%
- CCD and CMOS Imaging Sensors
- Advancements in PLL and VCO Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Radio Frequency Integrated Circuit Design
- Low-power high-performance VLSI design
- Photonic and Optical Devices
Biomedical Engineering top 10%
- Analog and Mixed-Signal Circuit Design

Papers in ⓘ

Biomedical Engineering 87
- Analog and Mixed-Signal Circuit Design 83
Electrical and Electronic Engineering 102
- CCD and CMOS Imaging Sensors 54
- Advancements in Semiconductor Devices and Circuit Design 39
- Advancements in PLL and VCO Technologies 27
- Low-power high-performance VLSI design 16
- Radio Frequency Integrated Circuit Design 13
- Photonic and Optical Devices 9

Co-authors: Zhihua Wang (80 shared papers)Chun Zhang (30 shared papers)Xiao Wang (9 shared papers)Hanjun Jiang (18 shared papers)Xuqiang Zheng (14 shared papers)Weitao Li (16 shared papers)Feng Zhao (6 shared papers)Shigang Yue (8 shared papers)
Journals: Journal of Semiconductors (14 papers)IEEE Transactions on Circuits and Systems I Regular Papers (4 papers)IEEE Transactions on Circuits & Systems II Express Briefs (3 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2 papers)IEEE Journal of Solid-State Circuits (2 papers)
Partner nations: China United Kingdom Singapore

In The Last Decade

Fule Li

97 papers receiving 493 citations

Peers

Countries citing papers authored by Fule Li

Since Specialization

Citations

This map shows the geographic impact of Fule Li's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Fule Li with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Fule Li more than expected).

Fields of papers citing papers by Fule Li

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Fule Li. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Fule Li. The network helps show where Fule Li may publish in the future.

Co-authors

The 25 scholars most cited alongside Fule Li, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Fule Li Line = papers co-authored together Fule Li links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 111 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO IEEE Journal of Solid-State Circuits ·Lingwei Zhang, Hanjun Jiang, Jianjun Wei, Jingjing Dong, Fule Li, Weitao Li, Jia Gao, Jianwei Cui, Baoyong Chi, Chun Zhang, Zhihua Wang	2013	47
2	A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process IEEE Transactions on Circuits and Systems I Regular Papers ·Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao, Shigang Yue, Chun Zhang, Zhihua Wang	2016	41
3	A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS IEEE Journal of Solid-State Circuits ·Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, Hanjun Jiang	2017	38
4	A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication IEEE Transactions on Industrial Electronics ·Peng Qi, Chun Zhang, Xijin Zhao, Xuguang Sun, Fule Li, Hong Chen, Zhihua Wang	2015	26
5	A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy IEEE Transactions on Circuits and Systems I Regular Papers ·Meng Ni, Xiao Wang, Fule Li, Woogeun Rhee, Zhihua Wang	2021	24
6	A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration IEEE Transactions on Circuits & Systems II Express Briefs ·Xiao Wang, Fule Li, Jia Wen, Zhihua Wang	2018	18
7	A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Peilin Yang, Xiao Wang, Chengwei Wang, Fule Li, Hanjun Jiang, Zhihua Wang	2020	14
8	A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs IEEE Transactions on Circuits & Systems II Express Briefs ·Xiao Wang, Fule Li, Zhihua Wang	2020	14
9	A RF remote-control transceiver with zero-standby power based on RFID technology Lin-Lin Chen, Ziqiang Wang, Jia Chen, Fule Li, Wenhan Hao, Bin Xiao, Chun Zhang, Zhihua Wang	2010	14
10	An 85mW 14-bit 150MS/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS Changyi Yang, Fule Li, Weitao Li, Xuan Wang, Zhihua Wang	2013	12
11	A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang	2017	11
12	A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang, Bin Wu	2012	11
13	A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS Lincoln Repository (University of Lincoln) ·Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang	2016	9
14	A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs Xiao Wang, Fule Li, Zhihua Wang	2016	9
15	An 8 bit 12 MS/s asynchronous successive approximation register ADC with an on-chip reference Journal of Semiconductors ·Yu Meng, Lipeng Wu, Fule Li, Zhihua Wang	2013	8
16	An ADC Input Buffer with Optimized Linearity Zekai Wu, Chengwei Wang, Yang Ding, Fule Li, Zhihua Wang	2018	7
17	High speed serial interface transceiver controller based on JESD204B Zhaoming Wu, Chun Zhang, Fule Li, Zhihua Wang	2016	7
18	A 10 GHz 56 fs _rms -integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang	2017	6
19	A 12Bit 800MS/s time-interleaving pipeline ADC in 65nm CMOS Meng Ni, Fule Li, Jia Zhou, Zhijun Wang, Chun Zhang, Xian Tang, Zhihua Wang	2016	6
20	A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang	2017	6

About Fule Li

Fule Li is a scholar working on Biomedical Engineering, Electrical and Electronic Engineering, Computer Networks and Communications, Bioengineering and Cellular and Molecular Neuroscience, having authored 111 papers that have together received 519 indexed citations. Recurring topics across this work include Analog and Mixed-Signal Circuit Design (83 papers), CCD and CMOS Imaging Sensors (54 papers), Advancements in Semiconductor Devices and Circuit Design (39 papers), Advancements in PLL and VCO Technologies (27 papers), Low-power high-performance VLSI design (16 papers), Radio Frequency Integrated Circuit Design (13 papers), Sensor Technology and Measurement Systems (12 papers) and Photonic and Optical Devices (9 papers). The work is most often cited by research in Electrical and Electronic Engineering (462 citations), Biomedical Engineering (345 citations), Hardware and Architecture (24 citations), Computer Networks and Communications (77 citations) and Media Technology (16 citations). Fule Li has collaborated with scholars based in China, United Kingdom and Singapore. Frequent co-authors include Zhihua Wang, Chun Zhang, Xiao Wang, Hanjun Jiang, Xuqiang Zheng, Weitao Li, Feng Zhao, Shigang Yue, Changyi Yang and Zhijun Wang. Their work appears in journals such as Journal of Semiconductors, IEEE Transactions on Circuits and Systems I Regular Papers, IEEE Transactions on Circuits & Systems II Express Briefs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Journal of Solid-State Circuits.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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