Debesh K. Das

866 total citations
103 papers, 517 citations indexed

About

Debesh K. Das is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computational Theory and Mathematics. According to data from OpenAlex, Debesh K. Das has authored 103 papers receiving a total of 517 indexed citations (citations by other indexed papers that have themselves been cited), including 82 papers in Electrical and Electronic Engineering, 52 papers in Hardware and Architecture and 32 papers in Computational Theory and Mathematics. Recurrent topics in Debesh K. Das's work include VLSI and Analog Circuit Testing (52 papers), Low-power high-performance VLSI design (39 papers) and Integrated Circuits and Semiconductor Failure Analysis (31 papers). Debesh K. Das is often cited by papers focused on VLSI and Analog Circuit Testing (52 papers), Low-power high-performance VLSI design (39 papers) and Integrated Circuits and Semiconductor Failure Analysis (31 papers). Debesh K. Das collaborates with scholars based in India, United States and Japan. Debesh K. Das's co-authors include Bhargab B. Bhattacharya, Hafizur Rahaman, Nur A. Touba, Dipak Kumar Kole, Arindam Banerjee, Michael Gössel, Susanta Chakraborty, Biplab K. Sikdar, Swagatam Das and S. Chakrabarti and has published in prestigious journals such as SHILAP Revista de lepidopterología, IEEE Transactions on Computers and Carbohydrate Research.

In The Last Decade

Debesh K. Das

91 papers receiving 468 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Debesh K. Das India 12 371 221 217 148 53 103 517
Malgorzata Chrzanowska-Jeske United States 14 575 1.5× 244 1.1× 248 1.1× 372 2.5× 70 1.3× 113 831
R. Leveugle France 9 299 0.8× 127 0.6× 213 1.0× 33 0.2× 44 0.8× 40 426
Chunshu Wu United States 8 111 0.3× 136 0.6× 66 0.3× 27 0.2× 42 0.8× 26 286
C. Zukowski United States 11 280 0.8× 109 0.5× 251 1.2× 71 0.5× 202 3.8× 50 505
Priyadarsan Patra United States 11 286 0.8× 76 0.3× 194 0.9× 44 0.3× 91 1.7× 50 443
Takashi Nanya Japan 12 352 0.9× 55 0.2× 310 1.4× 61 0.4× 254 4.8× 94 581
Ronald Scrofano United States 9 147 0.4× 32 0.1× 236 1.1× 98 0.7× 91 1.7× 17 320
Hidetaka Aoki Japan 7 189 0.5× 353 1.6× 51 0.2× 80 0.5× 70 1.3× 12 418
Kanupriya Gulati United States 11 285 0.8× 36 0.2× 273 1.3× 74 0.5× 115 2.2× 35 419
George F. Viamontes United States 10 387 1.0× 261 1.2× 210 1.0× 147 1.0× 12 0.2× 11 573

Countries citing papers authored by Debesh K. Das

Since Specialization
Citations

This map shows the geographic impact of Debesh K. Das's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Debesh K. Das with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Debesh K. Das more than expected).

Fields of papers citing papers by Debesh K. Das

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Debesh K. Das. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Debesh K. Das. The network helps show where Debesh K. Das may publish in the future.

Co-authorship network of co-authors of Debesh K. Das

This figure shows the co-authorship network connecting the top 25 collaborators of Debesh K. Das. A scholar is included among the top collaborators of Debesh K. Das based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Debesh K. Das. Debesh K. Das is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Das, Debesh K., et al.. (2025). Reducing delay and resistance of GNR based interconnect using insertion of buffers. Analog Integrated Circuits and Signal Processing. 123(1).
4.
Bhattacharya, Bhargab B., Debesh K. Das, Subhajit Chatterjee, & Hafizur Rahaman. (2024). Fault Testing in AI-Accelerators: A Review. 1–6.
5.
Das, Debesh K., et al.. (2023). A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issues. Analog Integrated Circuits and Signal Processing. 116(1-2). 49–67. 2 indexed citations
6.
Das, Debesh K., et al.. (2023). Design‐for‐testability for reversible logic circuits based on bit‐swapping. SHILAP Revista de lepidopterología. 5(2). 113–122.
7.
Das, Debesh K., et al.. (2022). A new online testing technique for reversible circuits. SHILAP Revista de lepidopterología. 3(1). 50–59. 3 indexed citations
8.
Kole, Dipak Kumar, et al.. (2021). DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits. Journal of Circuits Systems and Computers. 31(10). 1 indexed citations
9.
Das, Debesh K., et al.. (2020). A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects. ACM Journal on Emerging Technologies in Computing Systems. 16(3). 1–28. 3 indexed citations
10.
Giri, Chandan, et al.. (2019). Approach of genetic algorithm for power‐aware testing of 3D IC. IET Computers & Digital Techniques. 13(5). 383–396. 3 indexed citations
11.
Kole, Dipak Kumar, et al.. (2018). Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits. Journal of Circuits Systems and Computers. 28(12). 1950212–1950212. 2 indexed citations
12.
Das, Debesh K., et al.. (2016). Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. ACM Journal on Emerging Technologies in Computing Systems. 12(4). 1–29. 2 indexed citations
13.
Dasgupta, Parthasarathi, et al.. (2016). A rule-based approach for minimizing power dissipation of digital circuits. 1. 1–6. 2 indexed citations
14.
Das, Debesh K., et al.. (2013). Modular Design for Symmetric Functions Using Quantum Quaternary Logic. 13. 143–147. 1 indexed citations
15.
Das, Debesh K., et al.. (2013). A design for testability technique for quantum reversible circuits. 1–4. 6 indexed citations
16.
Rahaman, Hafizur & Debesh K. Das. (2006). Universal test set for detecting stuck-at and bridging faults in double fixed-polarity Reed–Muller programmable logic arrays. IEE Proceedings - Computers and Digital Techniques. 153(2). 109–109. 2 indexed citations
17.
Rahaman, Hafizur, Debesh K. Das, & Bhargab B. Bhattacharya. (2002). A New Synthesis of Symmetric Functions. Asia and South Pacific Design Automation Conference. 160–165. 4 indexed citations
18.
Roy, Samir, et al.. (2002). Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. Asia and South Pacific Design Automation Conference. 671–676. 2 indexed citations
19.
Sikdar, Biplab K., et al.. (2002). Enhancing BIST quality of sequential machines through degree-of-freedom analysis. 15. 285–290. 2 indexed citations
20.
Inoue, Tomoo, et al.. (2000). Test generation for acyclic sequential circuits with hold registers. International Conference on Computer Aided Design. 550–556. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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