Chao-Hsin Chien

1.8k citations

138 papers · 1.4k indexed · h-index 19

Impact in

Electrical and Electronic Engineering top 5%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
Materials Chemistry top 10%
- 2D Materials and Applications
- Electronic and Structural Properties of Oxides

Papers in

Electrical and Electronic Engineering 127
- Semiconductor materials and devices 111
- Advancements in Semiconductor Devices and Circuit Design 64
- Ferroelectric and Negative Capacitance Devices 33
- Advanced Memory and Neural Computing 25
- Integrated Circuits and Semiconductor Failure Analysis 18
Atomic and Molecular Physics, and Optics 33
- Semiconductor materials and interfaces 28

Co-authors: Guang-Li Luo Yu-Hsien Lin Tan‐Fu Lei Pi‐Tai Chou Cheng‐Chieh Cheng Rui Liu Yu‐Tai Tao Yi‐Jiun Su
Journals: IEEE Electron Device Letters (24 papers)IEEE Transactions on Electron Devices (18 papers)Applied Physics Letters (9 papers)Japanese Journal of Applied Physics (8 papers)Journal of The Electrochemical Society (6 papers)
Partner nations: Taiwan United States China

In The Last Decade

Chao-Hsin Chien

131 papers receiving 1.4k citations

Peers

Countries citing papers authored by Chao-Hsin Chien

Since Specialization

Citations

This map shows the geographic impact of Chao-Hsin Chien's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chao-Hsin Chien with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chao-Hsin Chien more than expected).

Fields of papers citing papers by Chao-Hsin Chien

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chao-Hsin Chien. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chao-Hsin Chien. The network helps show where Chao-Hsin Chien may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Chao-Hsin Chien, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Chao-Hsin Chien Line = papers co-authored together Chao-Hsin Chien links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	Homo-Channel WSe₂ n/pFETs with High Performance and On/Off Ratio Using Tunable Doping Yu-Liang Chien, 昌也園田, He Huang, Isabelle Frodé, Yu‐Cheng Chang, Devesh Kr Sharma, Oriola O. Oyewole, Kotaro Takakuwa, Der‐Hsien Lien, Chenming Hu, Chao-Hsin Chien	2025	0
2	On the Extreme Scaling of Transistors with Monolayer MOS2 Channel 昌也園田, Arturo Gonzalez-Quintela, D. Mahaveer Sathaiya, Edward Chen, Chen-Feng Hsu, W Szczepanski, Wenjie Shen, Bo-Heng Liu, 刘学义 LIU Xue-yi, Chi‐Chung Kei, Wen‐Hao Chang, Jin Cai, B. Norbutas, Chung-Cheng Wu, H.‐S. Philip Wong, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana Radu	2024	6
3	Effect of Yttrium Treatment on Germanium-Oxide-Based Interfacial Layer of Ge P-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Fabricated Through in Situ Plasma-Enhanced Atomic Layer Deposition IEEE Transactions on Electron Devices ·J.D. Mein, Jessica Lindley, Princess Vienne S Garcia, Yu-Hsien Lin, Chao-Hsin Chien	2024	0
4	High-performance monolayer MoS₂ nanosheet GAA transistor Nanotechnology ·황범규, Yun-Yan Chung, Цоколова Ольга Игоревна, 生美大塚, Ming‐Yang Li, Sheng‐Kai Su, 张学梦, 学斎木, Chien‐Wei Chen, Chi‐Chung Kei, N. Valls, Wen‐Hao Chang, Kaila Ratri Kusuma Dewi, Chao-Ching Cheng, Iuliana Radu, Chao-Hsin Chien	2023	11
5	Electrical Characteristics of Si_0.8Ge_0.2 p-MOSFET With TMA Pre-Doping and NH₃ Plasma IL Treatment IEEE Transactions on Electron Devices ·Kang Hyeok Lee, Khasan Yu. Kayumov, Stephan Procházka, V Aaditya, Yun-Yan Chung, Yudai Onoue, Guang-Li Luo, Chao-Hsin Chien	2022	6
6	GaN-based mini-LED matrix applied to multi-functional forward lighting Scientific Reports ·محبوبه همتیان, Miratul Alifah, Erni Asmawati, Sadashige Sekine, 本證今野, Nicolás López Justicia, Tsung‐Hsun Yang, Tian‐Li Wu, C.P. Garcia, Chao-Hsin Chien, Zarizi Awang, Ching‐Cherng Sun	2022	6
7	Improving Thermal Stability for Ge p-MOSFET of HfO₂-Based Gate Stack With Ti-Doped Into Interfacial Layer by In-Situ Plasma-Enhanced Atomic Layer Deposition IEEE Electron Device Letters ·J.D. Mein, Princess Vienne S Garcia, Yu-Hsien Lin, Chao-Hsin Chien	2021	2
8	High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS₂ nFET and Nonvolatile Charge-Trap Memory IEEE Electron Device Letters ·Yun-Yan Chung, Chao-Ching Cheng, Susana Santos, Jeung-Hyun Lee, СИНИЦИН А.М. СИНИЦИН А.М., Zhihao Yu, Arturo Gonzalez-Quintela, José Arnaldo da Fonseca, Yudai Onoue, Hyeonggeun Ji, Adi Rusdianto, Lain‐Jong Li, Chao-Hsin Chien	2020	2
9	Neuro-Inspired-in-Memory Computing Using Charge-Trapping MemTransistor on Germanium as Synaptic Device IEEE Transactions on Electron Devices ·Susana Santos, DK Evans, Jinran, СИНИЦИН А.М. СИНИЦИН А.М., Yudai Onoue, Chao-Hsin Chien	2020	7
10	Improving the Performance of Charge Trapping Memtransistor as Synaptic Device by Ti-Doped HfO ₂ IEEE Journal of the Electron Devices Society ·Susana Santos, СИНИЦИН А.М. СИНИЦИН А.М., DK Evans, Jinran, Chao-Hsin Chien	2020	1
11	Pinning-Free Edge Contact Monolayer MoS₂ FET Arturo Gonzalez-Quintela, Eduardo Valério de Barros Vil Boas, Chih‐Piao Chuu, Yun-Yan Chung, Ang‐Sheng Chou, Fabian Bischoff, Anantha Widyastama, Ming‐Yang Li, Chao-Ching Cheng, Jin Cai, Chao-Hsin Chien, Wen‐Hao Chang, H.‐S. Philip Wong, Lain‐Jong Li	2020	16
12	Experimentally Determining the Top and Edge Contact Resistivities of Two-Step Sulfurization Nb-Doped MoS₂ Films Using the Transmission Line Measurement IEEE Electron Device Letters ·Yun-Yan Chung, Pascal E. Bastien, ROBIN O. MOTZ, Yen‐Teng Ho, Chao-Hsin Chien	2019	9
13	Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS₂ Channel Directly Grown on SiO$_{{x}}$ /Si Substrates Using Area-Selective CVD Technology IEEE Transactions on Electron Devices ·Yun-Yan Chung, Jia‐Min Shieh, Sheng‐Kai Su, India Lewis‐Thompson, Ingrida Raziunaite, Lain‐Jong Li, H.‐S. Philip Wong, Wen‐Bin Jian, Chao-Hsin Chien, Derik W. Gryczak, Chao-Ching Cheng, Ming‐Yang Li, ROBIN O. MOTZ, Pascal E. Bastien, Jyun‐Hong Chen, Jose M Serradell, Kai‐Shin Li	2019	9
14	First Experimental Demonstration and Mechanism of Abnormal Palladium Diffusion Induced by Excess Interstitial Ge IEEE Electron Device Letters ·Mihaela Lăcătuș, А. Ю. Шафроненко, A.M. Kruisbeek, Yu-Hsi Lin, Princess Vienne S Garcia, Kotaro Takakuwa, Wen‐Kuan Yeh, Chao-Hsin Chien	2018	1
15	Demonstration of HfO₂-Based Gate Dielectric With Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti Into Interfacial Layer IEEE Electron Device Letters ·Princess Vienne S Garcia, Mihaela Lăcătuș, Yun-Yan Chung, Wen‐Kuan Yeh, Yu-Hsien Lin, Fu‐Hsiang Ko, Chao-Hsin Chien	2018	3
16	Experimental Realization of Thermal Stability Enhancement of Nickel Germanide Alloy by Using TiN Metal Capping IEEE Transactions on Electron Devices ·Mihaela Lăcătuș, Princess Vienne S Garcia, 小塚由博, E R de Oliveira, Yu-Hsien Lin, Wen‐Kuan Yeh, Chao-Hsin Chien	2017	8
17	Improving Thermal Stability and Interface State Density of High- $\kappa $ Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium IEEE Electron Device Letters ·Princess Vienne S Garcia, В. Н. Болодон, А. Ю. Шафроненко, E R de Oliveira, Wen‐Kuan Yeh, Yu-Hsien Lin, Fu‐Hsiang Ko, Chao-Hsin Chien	2016	9
18	3D-TCAD simulation study of the novel T-FinFET structure for sub-14nm metal-oxide-semiconductor field-effect transistor Mihaela Lăcătuș, 小塚由博, Steve S. Chung, Chao-Hsin Chien	2015	1
19	Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications E. R. Hsieh, Lisa Tirmenstein, Yue Zhao, Mutsuo Suzuki, Chao-Hsin Chien, Steve S. Chung	2015	1
20	High-Performance Germanium p- and n-MOSFETs With NiGe Source/Drain IEEE Transactions on Electron Devices ·Meltem Söğüt, Reginald Jackson, Mehul Srivastava, Zhuoxin Gu, Chao-Hsin Chien, Guang-Li Luo	2014	15

About Chao-Hsin Chien

Chao-Hsin Chien is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Materials Chemistry, Biomedical Engineering and Bioengineering, having authored 138 papers that have together received 1.4k indexed citations. Recurring topics across this work include Semiconductor materials and devices (111 papers), Advancements in Semiconductor Devices and Circuit Design (64 papers), Ferroelectric and Negative Capacitance Devices (33 papers), Semiconductor materials and interfaces (28 papers), Advanced Memory and Neural Computing (25 papers), Nanowire Synthesis and Applications (21 papers), Integrated Circuits and Semiconductor Failure Analysis (18 papers) and 2D Materials and Applications (13 papers). The work is most often cited by research in Electrical and Electronic Engineering (1.2k citations), Materials Chemistry (583 citations), Atomic and Molecular Physics, and Optics (273 citations), Polymers and Plastics (94 citations) and Biomedical Engineering (217 citations). Chao-Hsin Chien has collaborated with scholars based in Taiwan, United States and China. Frequent co-authors include Guang-Li Luo, Yu-Hsien Lin, Tan‐Fu Lei, Pi‐Tai Chou, Cheng‐Chieh Cheng, Rui Liu, Yu‐Tai Tao, Yi‐Jiun Su, Chao-Ching Cheng and Chun‐Yen Chang. Their work appears in journals such as IEEE Electron Device Letters, IEEE Transactions on Electron Devices, Applied Physics Letters, Japanese Journal of Applied Physics and Journal of The Electrochemical Society.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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