Ashish Venkat

598 total citations
27 papers, 387 citations indexed

About

Ashish Venkat is a scholar working on Hardware and Architecture, Computer Networks and Communications and Artificial Intelligence. According to data from OpenAlex, Ashish Venkat has authored 27 papers receiving a total of 387 indexed citations (citations by other indexed papers that have themselves been cited), including 19 papers in Hardware and Architecture, 14 papers in Computer Networks and Communications and 14 papers in Artificial Intelligence. Recurrent topics in Ashish Venkat's work include Parallel Computing and Optimization Techniques (15 papers), Security and Verification in Computing (9 papers) and Advanced Data Storage Technologies (9 papers). Ashish Venkat is often cited by papers focused on Parallel Computing and Optimization Techniques (15 papers), Security and Verification in Computing (9 papers) and Advanced Data Storage Technologies (9 papers). Ashish Venkat collaborates with scholars based in United States, Serbia and India. Ashish Venkat's co-authors include Dean M. Tullsen, Mohammadkazem Taram, Kevin Skadron, Hovav Shacham, David Roberts, Vilas Sridharan, Manish Gupta, Rajesh K. Gupta, Amit Kumar Mishra and Mircea R. Stan and has published in prestigious journals such as ACM SIGPLAN Notices, IEEE Micro and IEEE Computer Architecture Letters.

In The Last Decade

Ashish Venkat

26 papers receiving 370 citations

Peers

Ashish Venkat
Dimitrios Skarlatos United States
Juan del Cuvillo United States
Gururaj Saileshwar United States
Geoff Pike United States
Lluís Vilanova Spain
Lois Orosa Switzerland
Todd Sproull United States
Claudio Canella Austria
Siddhartha Chhabra United States
Gyungho Lee United States
Dimitrios Skarlatos United States
Ashish Venkat
Citations per year, relative to Ashish Venkat Ashish Venkat (= 1×) peers Dimitrios Skarlatos

Countries citing papers authored by Ashish Venkat

Since Specialization
Citations

This map shows the geographic impact of Ashish Venkat's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ashish Venkat with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ashish Venkat more than expected).

Fields of papers citing papers by Ashish Venkat

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ashish Venkat. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ashish Venkat. The network helps show where Ashish Venkat may publish in the future.

Co-authorship network of co-authors of Ashish Venkat

This figure shows the co-authorship network connecting the top 25 collaborators of Ashish Venkat. A scholar is included among the top collaborators of Ashish Venkat based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ashish Venkat. Ashish Venkat is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Venkat, Ashish, et al.. (2024). Architectural Modeling and Benchmarking for Digital DRAM PIM. 247–261. 1 indexed citations
2.
3.
Zhou, Minxuan, et al.. (2023). Abakus: Accelerating k -mer Counting with Storage Technology. ACM Transactions on Architecture and Code Optimization. 21(1). 1–26. 2 indexed citations
4.
5.
Taram, Mohammadkazem, Ashish Venkat, & Dean M. Tullsen. (2022). Mitigating Speculative Execution Attacks via Context-Sensitive Fencing. IEEE Design and Test. 39(4). 49–57. 2 indexed citations
6.
Skadron, Kevin, et al.. (2021). Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching. 251–264. 22 indexed citations
7.
Taram, Mohammadkazem, et al.. (2021). I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches. 361–374. 33 indexed citations
8.
Venkat, Ashish, et al.. (2020). CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities. 762–775. 23 indexed citations
9.
Taram, Mohammadkazem, Ashish Venkat, & Dean M. Tullsen. (2019). Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management. IEEE Micro. 39(3). 75–83. 4 indexed citations
10.
Taram, Mohammadkazem, Dean M. Tullsen, Ashish Venkat, et al.. (2019). Fast and Efficient Deployment of Security Defenses Via Context Sensitive Decoding. 1 indexed citations
11.
Venkat, Ashish, et al.. (2019). Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures. 51–60. 2 indexed citations
12.
Taram, Mohammadkazem, Ashish Venkat, & Dean M. Tullsen. (2018). Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency. 624–637. 14 indexed citations
13.
Venkat, Ashish. (2018). Breaking the ISA Barrier in Modern Computing. eScholarship (California Digital Library). 4 indexed citations
14.
Venkat, Ashish, et al.. (2016). HIPStR. ACM SIGARCH Computer Architecture News. 44(2). 727–741. 1 indexed citations
15.
Venkat, Ashish, et al.. (2016). HIPStR. 727–741. 19 indexed citations
16.
Venkat, Ashish & Dean M. Tullsen. (2014). Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor. 121–132. 27 indexed citations
17.
Venkat, Ashish & Dean M. Tullsen. (2014). Harnessing ISA diversity. ACM SIGARCH Computer Architecture News. 42(3). 121–132. 60 indexed citations
18.
Venkat, Ashish, et al.. (2012). Execution migration in a heterogeneous-ISA chip multiprocessor. 261–272. 55 indexed citations
19.
Venkat, Ashish, et al.. (2012). Execution migration in a heterogeneous-ISA chip multiprocessor. ACM SIGARCH Computer Architecture News. 40(1). 261–272. 4 indexed citations
20.
Venkat, Ashish, et al.. (2012). Execution migration in a heterogeneous-ISA chip multiprocessor. ACM SIGPLAN Notices. 47(4). 261–272. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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