Armin Tajalli

1.4k total citations
100 papers, 884 citations indexed

About

Armin Tajalli is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Computer Networks and Communications. According to data from OpenAlex, Armin Tajalli has authored 100 papers receiving a total of 884 indexed citations (citations by other indexed papers that have themselves been cited), including 97 papers in Electrical and Electronic Engineering, 63 papers in Biomedical Engineering and 4 papers in Computer Networks and Communications. Recurrent topics in Armin Tajalli's work include Analog and Mixed-Signal Circuit Design (62 papers), Advancements in PLL and VCO Technologies (49 papers) and Low-power high-performance VLSI design (42 papers). Armin Tajalli is often cited by papers focused on Analog and Mixed-Signal Circuit Design (62 papers), Advancements in PLL and VCO Technologies (49 papers) and Low-power high-performance VLSI design (42 papers). Armin Tajalli collaborates with scholars based in Switzerland, United States and Iran. Armin Tajalli's co-authors include Yusuf Leblebici, E.J. Brauer, Eric A. Vittoz, M. Atarodi, Farzan Jazaeri, Jean-Michel Sallèse, Arnout Beckers, Massimo Alioto, Paul Müller and Ali Hormati and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Electronics Letters and IEEE Transactions on Circuits and Systems I Regular Papers.

In The Last Decade

Armin Tajalli

90 papers receiving 845 citations

Peers

Countries citing papers authored by Armin Tajalli

Since Specialization

Citations

This map shows the geographic impact of Armin Tajalli's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Armin Tajalli with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Armin Tajalli more than expected).

Fields of papers citing papers by Armin Tajalli

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Armin Tajalli. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Armin Tajalli. The network helps show where Armin Tajalli may publish in the future.

Co-authorship network of co-authors of Armin Tajalli

This figure shows the co-authorship network connecting the top 25 collaborators of Armin Tajalli. A scholar is included among the top collaborators of Armin Tajalli based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Armin Tajalli. Armin Tajalli is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Digital Background Calibration Circuit for Coarse-Fine Timing Mismatch in VCO-Based ADCs 2024 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown), Armin Tajalli, Yen‐Cheng Kuan, Shiuh-Hua Wood Chiang	0
2	Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers 2024 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown), Shiuh-Hua Wood Chiang, Armin Tajalli	3
3	Noise-Aware FET Circuit Design Based on C/I_D-Invariant 2023 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown), (unknown), (unknown), Farzan Jazaeri, Armin Tajalli	3
4	Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology 2023 ·(unknown), (unknown), Armin Tajalli	1
5	Systematic Design of Loop Circuit Topologies Using C/I _DS Methodology 2022 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown), (unknown), Armin Tajalli	4
6	A Controllable K_VCO Ring VCO Topology 2021 ·(unknown), Armin Tajalli	2
7	A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors 2020 ·(unknown), Armin Tajalli, Mohammad Taherzadeh‐Sani	5
8	JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS 2019 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·(unknown), (unknown), Armin Tajalli, Andreas Burg, Yusuf Leblebici	7
9	A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces 2016 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·(unknown), (unknown), Armin Tajalli, Yusuf Leblebici	2
10	Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits 2014 ·IEEE Transactions on Circuits and Systems I Regular Papers ·Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici	12
11	Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter 2011 ·IEEE Transactions on Circuits & Systems II Express Briefs ·Armin Tajalli, Yusuf Leblebici	15
12	Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits 2010 ·Design, Automation, and Test in Europe ·Armin Tajalli, Yusuf Leblebici	8
13	Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution 2010 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Armin Tajalli, Yusuf Leblebici	1
14	Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems 2009 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Armin Tajalli, Yusuf Leblebici	10
15	Pico-Watt Source-Coupled Logic Circuits 2008 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Armin Tajalli, Yusuf Leblebici, E.J. Brauer	2
16	Implementing ultra-high-value floating tunable CMOS resistors 2008 ·Electronics Letters ·Armin Tajalli, (unknown), E.J. Brauer	90
17	A ¼ Rate Linear Phase Detector for PLL-Based CDR Circuits 2006 ·Mohammad Saffari, M. Atarodi, Armin Tajalli	1
18	A fractional delay-locked loop for on chip clock generation applications 2005 ·(unknown), Armin Tajalli, M. Atarodi	1
19	A fractional delay-locked loop for on chip clock generation applications 2005 ·(unknown), Armin Tajalli, M. Atarodi	1
20	A duty cycle control circuit for high speed applications 2004 ·Armin Tajalli, (unknown), M. Atarodi	5

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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