This map shows the geographic impact of research published in VLSI design. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by papers published in VLSI design with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites VLSI design more than expected).
This network shows the impact of papers published in VLSI design. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers published in VLSI design.
About VLSI design
The 615 papers published in VLSI design in the last decades have received a total of 4.5k indexed citations . Papers published in VLSI design usually cover Hardware and Architecture (217 papers), Electrical and Electronic Engineering (446 papers) and Computer Networks and Communications (109 papers) specifically the topics of Advancements in Semiconductor Devices and Circuit Design (134 papers), VLSI and Analog Circuit Testing (124 papers), Low-power high-performance VLSI design (120 papers), VLSI and FPGA Design Techniques (106 papers), Embedded Systems Design Techniques (94 papers), Semiconductor materials and devices (77 papers), Interconnection Networks and Systems (76 papers) and Integrated Circuits and Semiconductor Failure Analysis (54 papers). The most active scholars publishing in VLSI design are Anton Arnold, Vipin Kumar, George Karypis, Henry Fuchs, Günter Mahler, L. Jóźwiak, Carl L. Gardner, Andreas Hansson, Kees Goossens and A. Rădulescu.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive
bibliographic database. While OpenAlex provides broad and valuable coverage of the global
research landscape, it—like all bibliographic datasets—has inherent limitations. These include
incomplete records, variations in author disambiguation, differences in journal indexing, and
delays in data updates. As a result, some metrics and network relationships displayed in
Rankless may not fully capture the entirety of a scholar's output or impact.