Viresh Paruthi

946 total citations
17 papers, 487 citations indexed

About

Viresh Paruthi is a scholar working on Hardware and Architecture, Computational Theory and Mathematics and Electrical and Electronic Engineering. According to data from OpenAlex, Viresh Paruthi has authored 17 papers receiving a total of 487 indexed citations (citations by other indexed papers that have themselves been cited), including 14 papers in Hardware and Architecture, 14 papers in Computational Theory and Mathematics and 10 papers in Electrical and Electronic Engineering. Recurrent topics in Viresh Paruthi's work include Formal Methods in Verification (14 papers), Radiation Effects in Electronics (8 papers) and VLSI and Analog Circuit Testing (7 papers). Viresh Paruthi is often cited by papers focused on Formal Methods in Verification (14 papers), Radiation Effects in Electronics (8 papers) and VLSI and Analog Circuit Testing (7 papers). Viresh Paruthi collaborates with scholars based in United States, Germany and Israel. Viresh Paruthi's co-authors include Andreas Kuehlmann, Malay Ganai, Jason Baumgartner, Christian Jacobi, Ranga Vemuri, Najme Mansouri, L. A. Lastras-Montaño, А. А. Львов, Barry Trager and Bishop Brock and has published in prestigious journals such as IBM Journal of Research and Development, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Formal Methods in System Design.

In The Last Decade

Viresh Paruthi

16 papers receiving 436 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Viresh Paruthi United States	8	367	280	233	142	103	17	487
E. Goldberg United States	7	315 0.9×	198 0.7×	141 0.6×	151 1.1×	141 1.4×	10	427
Yung-Te Lai United States	9	337 0.9×	266 0.9×	176 0.8×	89 0.6×	88 0.9×	9	441
H.J. Touati United States	12	300 0.8×	482 1.7×	359 1.5×	89 0.6×	87 0.8×	16	648
Sean Safarpour Canada	12	199 0.5×	230 0.8×	158 0.7×	138 1.0×	47 0.5×	29	347
Thomas R. Shiple United States	9	350 1.0×	314 1.1×	134 0.6×	136 1.0×	95 0.9×	17	471
Richard Raimi United States	4	318 0.9×	137 0.5×	67 0.3×	201 1.4×	138 1.3×	6	418
Carl Pixley United States	16	415 1.1×	481 1.7×	323 1.4×	203 1.4×	106 1.0×	46	681
Carl-Johan H. Seger Canada	10	382 1.0×	276 1.0×	143 0.6×	167 1.2×	100 1.0×	18	471
Mark D. Aagaard Canada	12	250 0.7×	158 0.6×	121 0.5×	98 0.7×	168 1.6×	47	389
Jawahar Jain United States	9	235 0.6×	207 0.7×	142 0.6×	100 0.7×	74 0.7×	21	329

Countries citing papers authored by Viresh Paruthi

Since Specialization

Citations

This map shows the geographic impact of Viresh Paruthi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Viresh Paruthi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Viresh Paruthi more than expected).

Fields of papers citing papers by Viresh Paruthi

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Viresh Paruthi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Viresh Paruthi. The network helps show where Viresh Paruthi may publish in the future.

Co-authorship network of co-authors of Viresh Paruthi

This figure shows the co-authorship network connecting the top 25 collaborators of Viresh Paruthi. A scholar is included among the top collaborators of Viresh Paruthi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Viresh Paruthi. Viresh Paruthi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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17 of 17 papers shown

Mackin, Charles, et al.. (2024). Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization. 1–10. 2 indexed citations

Paruthi, Viresh, et al.. (2014). Automatic Verification of Floating Point Units. 1–6. 2 indexed citations

Львов, А. А., et al.. (2014). Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry. Formal Methods in System Design. 45(2). 189–212. 3 indexed citations

Львов, А. А., et al.. (2012). Formal verification of error correcting circuits using computational algebraic geometry. 141–148. 5 indexed citations

Sawada, J., et al.. (2011). Hybrid verification of a hardware modular reduction engine. 207–214. 1 indexed citations

Roesner, Wolfgang, et al.. (2011). Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems. IBM Journal of Research and Development. 55(3). 10:1–10:17. 14 indexed citations

Paruthi, Viresh, et al.. (2010). Formal verification of arbiters using property strengthening and underapproximations. 21–24. 3 indexed citations

Paruthi, Viresh. (2010). Large-scale application of formal verification: from fiction to fact. 175–180. 1 indexed citations

Paruthi, Viresh, et al.. (2009). Formal verification of correctness and performance of random priority-based arbiters. 101–107. 7 indexed citations

10.

Baumgartner, Jason, et al.. (2006). Scalable Sequential Equivalence Checking across Arbitrary Design Transformations. 259–266. 43 indexed citations

11.

Jacobi, Christian, et al.. (2005). Automatic Formal Verification of Fused-Multiply-Add FPUs. Design, Automation, and Test in Europe. 1298–1303. 25 indexed citations

12.

Baumgartner, Jason, et al.. (2005). Exploiting suspected redundancy without proving it. 463–463. 27 indexed citations

13.

Paruthi, Viresh, et al.. (2005). Exploiting suspected redundancy without proving it. 4 indexed citations

14.

Kuehlmann, Andreas, et al.. (2002). Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21(12). 1377–1394. 195 indexed citations

15.

Paruthi, Viresh & Andreas Kuehlmann. (2002). Equivalence checking combining a structural SAT-solver, BDDs, and simulation. 459–464. 30 indexed citations

16.

Paruthi, Viresh, Najme Mansouri, & Ranga Vemuri. (2002). Automatic data path abstraction for verification of large scale designs. 192–194. 16 indexed citations

17.

Kuehlmann, Andreas, Malay Ganai, & Viresh Paruthi. (2001). Circuit-based Boolean Reasoning. 232–237. 109 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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