Toshihiro Katashita
- Hardware and Architecture top 1%
- Physical Unclonable Functions (PUFs) and Hardware Security 26
- VLSI and Analog Circuit Testing 3
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- Neuroscience and Neural Engineering 4
- Artificial Intelligence top 10%
- Cryptographic Implementations and Security 17
- Security and Verification in Computing 5
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- Integrated Circuits and Semiconductor Failure Analysis 7
- Advanced Memory and Neural Computing 4
- Signal Processing top 10%
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- Chaos-based Image/Signal Encryption 9
Toshihiro Katashita
33 papers receiving 521 citations
Peers
Comparison fields: 5 of 26
- Hardware and Architecture 463
- Cellular and Molecular Neuroscience 166
- Artificial Intelligence 191
- Electrical and Electronic Engineering 321
- Signal Processing 57
Countries citing papers authored by Toshihiro Katashita
This map shows the geographic impact of Toshihiro Katashita's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Toshihiro Katashita with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Toshihiro Katashita more than expected).
Fields of papers citing papers by Toshihiro Katashita
This network shows the impact of papers produced by Toshihiro Katashita. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Toshihiro Katashita. The network helps show where Toshihiro Katashita may publish in the future.
Co-authorship network
The 25 scholars most cited alongside Toshihiro Katashita, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2020 | 5 | |
| 2 | On Machine Learning Attack Tolerance for PUF-based Device Authentication System | 2019 | 2 |
| 3 | 2018 | 1 | |
| 4 | 2017 | 3 | |
| 5 | 2016 | 1 | |
| 6 | 2014 | 47 | |
| 7 | 2014 | 1 | |
| 8 | Performance Evaluation of Physical Unclonable FUnctions on Kintex-7 FPGA | 2013 | 4 |
| 9 | PUF evaluation with post-processing and modified modeling attack | 2013 | 0 |
| 10 | 2013 | 3 | |
| 11 | 2013 | 7 | |
| 12 | 2011 | 10 | |
| 13 | 2011 | 36 | |
| 14 | Magnetic Field Measurement for Side-channel Analysis Environment | 2010 | 0 |
| 15 | Quantitative Performance Evaluation of Arbiter PUFs on FPGAs | 2010 | 2 |
| 16 | Performance Evaluation for PUF-based Authentication Systems with Shift Post-processing | 2010 | 0 |
| 17 | FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet(Reconfigurable System and Applications, Reconfigurable Systems) | 2007 | 1 |
| 18 | 2007 | 21 | |
| 19 | 2006 | 2 | |
| 20 | 2006 | 8 |
About Toshihiro Katashita
Toshihiro Katashita is a scholar working on Hardware and Architecture, Artificial Intelligence and Computer Vision and Pattern Recognition, having authored 37 papers that have together received 532 indexed citations. Recurring topics across this work include Physical Unclonable Functions (PUFs) and Hardware Security (26 papers), Cryptographic Implementations and Security (17 papers), Chaos-based Image/Signal Encryption (9 papers), Integrated Circuits and Semiconductor Failure Analysis (7 papers), Security and Verification in Computing (5 papers), Advanced Memory and Neural Computing (4 papers), Neuroscience and Neural Engineering (4 papers) and VLSI and Analog Circuit Testing (3 papers). The work is most often cited by research in Hardware and Architecture (463 citations), Cellular and Molecular Neuroscience (166 citations) and Artificial Intelligence (191 citations). Toshihiro Katashita has collaborated with scholars based in Japan, France and Belgium. Frequent co-authors include Yohei Hori, Akashi Satoh, Takahiro Yoshida, Hyunho Kang, Akihiko Sasaki, Manabu Hagiwara, Keiichi Iwamura, Kazukuni Kobara, Takeshi Sugawara and Naofumi Homma. Their work appears in journals such as IEEE Access, Organic Electronics and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.