Gu-Yeon Wei
- Hardware and Architecture top 0.1%
- Parallel Computing and Optimization Techniques 82
- Embedded Systems Design Techniques 37
- Computer Networks and Communications top 0.5%
- Interconnection Networks and Systems 25
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- Low-power high-performance VLSI design 58
- Advanced Memory and Neural Computing 32
- Advancements in PLL and VCO Technologies 31
- Semiconductor materials and devices 22
- Information Systems top 0.5%
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- Analog and Mixed-Signal Circuit Design 28
- Co-authors
- David BrooksWonyoung KimMeeta S. GuptaBrandon ReagenSae Kyu LeeMichael KarpelsonXiaoyao LiangMark Horowitz
- Cited by
- Hardware and ArchitectureComputer Networks and CommunicationsElectrical and Electronic Engineering
- Journals
- IEEE Journal of Solid-State Circuits (15 papers)IEEE Micro (13 papers)IEEE Computer Architecture Letters (4 papers)
- Partner nations
- United StatesUnited KingdomSouth Korea
In The Last Decade
Gu-Yeon Wei
220 papers receiving 7.8k citations
Hit Papers
Peers
Comparison fields: 5 of 114
- Hardware and Architecture 3.3k
- Computer Networks and Communications 2.7k
- Electrical and Electronic Engineering 4.9k
- Computer Vision and Pattern Recognition 884
- Information Systems 813
Countries citing papers authored by Gu-Yeon Wei
This map shows the geographic impact of Gu-Yeon Wei's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Gu-Yeon Wei with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Gu-Yeon Wei more than expected).
Fields of papers citing papers by Gu-Yeon Wei
This network shows the impact of papers produced by Gu-Yeon Wei. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Gu-Yeon Wei. The network helps show where Gu-Yeon Wei may publish in the future.
Co-authorship network
The 25 scholars most cited alongside Gu-Yeon Wei, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2024 | 2 | |
| 2 | 2024 | 0 | |
| 3 | 2023 | 2 | |
| 4 | 2023 | 4 | |
| 5 | 2023 | 11 | |
| 6 | 2022 | 12 | |
| 7 | 2022 | 5 | |
| 8 | 2022 | 5 | |
| 9 | 2019 | 7 | |
| 10 | 2019 | 2 | |
| 11 | 2018 | 69 | |
| 12 | 2017 | 48 | |
| 13 | 14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications | 2017 | 56 |
| 14 | 2017 | 8 | |
| 15 | 2016 | 18 | |
| 16 | 2009 | 29 | |
| 17 | R 6T SRAM 3T1D DRAM L1 D C C P V | 2008 | 24 |
| 18 | 2008 | 3 | |
| 19 | Process Variation Tolerant 3T1D-Based Cache Architecturesbreakdown → | 2007 | 383 |
| 20 | 2004 | 4 |
About Gu-Yeon Wei
Gu-Yeon Wei is a scholar working on Hardware and Architecture, Computer Networks and Communications, Electrical and Electronic Engineering, Computer Vision and Pattern Recognition and Artificial Intelligence, having authored 228 papers that have together received 8.1k indexed citations. Recurring topics across this work include Parallel Computing and Optimization Techniques (82 papers), Low-power high-performance VLSI design (58 papers), Embedded Systems Design Techniques (37 papers), Advanced Memory and Neural Computing (32 papers), Advancements in PLL and VCO Technologies (31 papers), Analog and Mixed-Signal Circuit Design (28 papers), Interconnection Networks and Systems (25 papers) and Semiconductor materials and devices (22 papers). The work is most often cited by research in Hardware and Architecture (3.3k citations), Computer Networks and Communications (2.7k citations), Electrical and Electronic Engineering (4.9k citations), Computer Vision and Pattern Recognition (884 citations) and Information Systems (813 citations). Gu-Yeon Wei has collaborated with scholars based in United States, United Kingdom and South Korea. Frequent co-authors include David Brooks, Wonyoung Kim, Meeta S. Gupta, Brandon Reagen, Sae Kyu Lee, Michael Karpelson, Xiaoyao Liang, Mark Horowitz, David J. Brooks and Robert J. Wood. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Micro, IEEE Computer Architecture Letters, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and IEEE Transactions on Circuits & Systems II Express Briefs.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.